Hi Roger,
I'm looking at the dra7.dtsi to try to understand the base addresses,
and I'm rather confused about the node addresses vs the reg addresses
for both dcan1 and dcan2.
Could you clarify why the reg address and node addresses are so
different for both, and where I might find the TRM that describes
these addresses? All I could find was a datasheet that didn't give
any info about the IP or the base addresses, but I'd really like to
understand what the *real* addresses are for this.
I'm pinging you because you're the author of the original commit[1],
but feel free to pass along to anyone else who might be able to help.
Thanks,
Kevin
[1]
commit 9ec49b9f2b43
Author: Roger Quadros <rogerq@xxxxxx>
Date: Fri Aug 15 16:08:36 2014 +0300
ARM: dts: DRA7: Add DCAN nodes
The SoC supports 2 DCAN nodes. Add them.
Signed-off-by: Roger Quadros <rogerq@xxxxxx>
Signed-off-by: Tony Lindgren <tony@xxxxxxxxxxx>
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 960b2c5e0df1..63bf99be1762 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -40,6 +40,8 @@
serial9 = &uart10;
ethernet0 = &cpsw_emac0;
ethernet1 = &cpsw_emac1;
+ d_can0 = &dcan1;
+ d_can1 = &dcan2;
};
timer {
@@ -1400,6 +1402,25 @@
};
};
+ dcan1: can@481cc000 {
+ compatible = "ti,dra7-d_can";
+ ti,hwmods = "dcan1";
+ reg = <0x4ae3c000 0x2000>;
+ syscon-raminit = <&dra7_ctrl_core 0x558 0>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dcan1_sys_clk_mux>;
+ status = "disabled";
+ };
+
+ dcan2: can@481d0000 {
+ compatible = "ti,dra7-d_can";
+ ti,hwmods = "dcan2";
+ reg = <0x48480000 0x2000>;
+ syscon-raminit = <&dra7_ctrl_core 0x558 1>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clkin1>;
+ status = "disabled";
+ };
};
};
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