On Wed, 27 May 2009 16:33:22 +0200
Janusz Krzysztofik <jkrzyszt@xxxxxxxxxxxx> wrote:
> >> - .srgr2 = GSYNC | CLKSP | FSGM | FPER(DEFAULT_BITPERSAMPLE
> >> * 2 - 1),
> >> + .srgr2 = GSYNC,
> >>
> >> - .pcr0 = CLKXP | CLKRP, /* mcbsp: slave */
> >>
...
> > I wonder why the frame sync period (FWID) wasn't set in that
> > original patch but probably McBSP is able to work without :-)
>
> from linux-2.6.29/sound/soc/omap/omap-mcbsp.c:
> switch (mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
> case SND_SOC_DAIFMT_I2S:
> regs->srgr2 |= FPER(wlen * 2 - 1);
> regs->srgr1 |= FWID(wlen - 1);
> break;
> case SND_SOC_DAIFMT_DSP_B:
> regs->srgr2 |= FPER(wlen * channels - 1);
> regs->srgr1 |= FWID(0);
> break;
> }
>
> So it looks like in case of SND_SOC_DAIFMT_DSP_B, FWID is not set,
> only FPER. However, in the original patch, FPER was not set either.
>
Sorry, my short above. Obviously I was wondering missing FPER setting
in original patch which defines the length of frame sync period. FWID
defines the length of frame sync pulse (n.o. bit clock pulses - 1).
Frame sync pulse length is half of the period in I2S and 1-bit clock
cycle in DSP_B. WM9713 has nice drawings about different formats. Look
pages 29 and 30.
http://www.wolfsonmicro.com/uploads/documents/en/WM9713.pdf
> I hope DMA chaining is not an issue here. If I remove the DMA
> chaining workaround from the original patch, I get signle DMA
> interrupts, so that is better than none that I get with my patch.
>
I think chaining is not issue if you are not getting any interrupt.
Basically if DMA transfer is working but DMA restarting is not then
there should be one completed buffer transfer and >= 2 interrupts from
completed periods.
--
Jarkko
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