Kalle Jokiniemi <kalle.jokiniemi@xxxxxxxxx> writes:
> The secure sram context save uses dma channels 0 and 1.
> In order to avoid collision between kernel DMA transfers and
> ROM code dma transfers, we need to reserve DMA channels 0
> 1 on high security devices.
>
> A bug in ROM code leaves dma irq status bits uncleared.
> Hence those irq status bits need to be cleared when restoring
> DMA context after off mode.
>
> There was also a faulty parameter given to PPA in the secure
> ram context save assembly code, which caused interrupts to
> be enabled during secure ram context save. This caused the
> save to fail sometimes, which resulted the saved context
> to be corrupted, but also left DMA channels in secure mode.
> The secure mode DMA channels caused "DMA secure error with
> device 0" errors to be displayed.
>
> Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@xxxxxxxxx>
> Signed-off-by: Jouni Hogander <jouni.hogander@xxxxxxxxx>
Thanks, pushing after fixing this minor checkpatch warning:
WARNING: braces {} are not necessary for single statement blocks
#82: FILE: arch/arm/plat-omap/dma.c:2337:
+ if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
+ dma_write(0x3 , IRQSTATUS_L0);
+ }
Kevin
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