On Fri, Jan 29, 2016 at 11:26:53PM -0500, David Rivshin (Allworx) wrote:
> From: David Rivshin <drivshin@xxxxxxxxxxx>
>
> When converting period and duty_cycle from nanoseconds to fclk cycles,
> the error introduced by the integer division can be appreciable, especially
> in the case of slow fclk or short period. Use DIV_ROUND_CLOSEST_ULL() so
> that the error is kept to +/- 0.5 clock cycles.
>
> Fixes: 6604c6556db9 ("pwm: Add PWM driver for OMAP using dual-mode timers")
> Signed-off-by: David Rivshin <drivshin@xxxxxxxxxxx>
> ---
> drivers/pwm/pwm-omap-dmtimer.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
Applied, thanks.
Thierry
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