* Tero Kristo <t-kristo@xxxxxx> [151216 01:00]: > Errata i810 states that DPLL controller can get stuck while transitioning > to a power saving state, while its M/N ratio is being re-programmed. > > As a workaround, before re-programming the M/N ratio, SW has to ensure > the DPLL cannot start an idle state transition. SW can disable DPLL > idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request > active by setting a dependent clock domain in SW_WKUP. > > This errata is known to impact OMAP5 and DRA7 chips, but lets enable it > unconditionally to avoid any potential problems with earlier generation > SoCs also. > > Signed-off-by: Tero Kristo <t-kristo@xxxxxx> > --- > v2: made the fix to be applied unconditionally on all OMAP3+ SoCs Thanks looks good to me now: Acked-by: Tony Lindgren <tony@xxxxxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
