On 13/10/15 10:55, Tero Kristo wrote: > TRMs are correct, 3630 does not have x2 multiplier after DPLL4. > > In the clock data, dpll4_m4x2 path is an x1 multiplier on omap3630, it > is easier to represent this in DT than completely remove the dpll4_*x2 > nodes for omap36xx. This is how it was already before the DT clocks. > > Here is a copy paste from clock debug data on omap36xx where you see the > rate for the whole dpll4_m4 path is 96MHz: > > dpll4_m4_ck 0 1 96000000 > 0 0 > dpll4_m4x2_mul_ck 0 1 96000000 > 0 0 > dpll4_m4x2_ck 0 1 96000000 > 0 0 > dss1_alwon_fck_3430es2 0 4 > 96000000 0 0 > > And same on omap34xx (not sure why the clock rate is totally different > here though, but you see the x2 applied): > > dpll4_m4_ck 0 1 216000000 > 0 > 0 > dpll4_m4x2_mul_ck 0 1 432000000 > 0 0 > dpll4_m4x2_ck 0 1 432000000 > 0 > 0 Ok, so the clock data in the DT and the data in the dss are in sync and according to the TRM. So the patch in this thread is not correct. How about 3730? Are we sure the dpll clocks are the same for 3730 and 3630? So both 3730 and 3630 are failing the same way? Hmm, wait... Beagle-xm has DM3730, right? It was working fine for me (until the whole board died, and you can't get new ones anymore =(). Tomi
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