On Sat, Feb 21, 2015 at 06:11:29PM +0100, Thomas Niederprüm wrote: > This patch fixes faulty behaviour in a setup where the input clock for the > SRG is fed through the CLKR/CLKX pin but the McBSP is configured to be > master (SND_SOC_DAIFMT_CBS_CFS). In that case of course CLKR/CLKX must > not be configured as output pin. Otherwise the input clock is messed up > horribly. Applied, but please as covered in SubmittingPatches word wrap your changelog entries to less than 80 columns - this is especially important for the subject line. Please also remember to CC maintainers on patches, the reason you've had to resend this patch is that you didn't originally send it to me (which means the RESEND tag both makes the subject line even longer and makes me a bit grumpy).
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