03 дек. 2014 г., в 18:49, Felipe Balbi <balbi@xxxxxx> написал(а): > >> 2. I want to avoid changing fifos before message submission, because >> IP can start receiving message in a slave mode (race). > > I2C is not full-duplex. There's no way it will receive any data while > you're transmitting, right ? > I2C is half duplex, right. But, IP work in slave receiver and master transmitter modes. And IP switch to slave receiver mode after master transfer (simply clear MST bit and ready for reception and that TRM state about). And question sounds like: what happen if we reset or change FIFO threshold value (in order to submit new master transfer) when IP start receiving data to the fifo. How many bytes we have to read on RRDY? That race I'am talking about. And there is only one place where race couldn't happen: it's ISR (thread). So I want to move almost all master initialization code into ISR. >> 3. dev->threshold is changed in range 1-fifo_size/2. So instead of RDR >> we get RRDY and for messages larger then fifo_size/2 we still get RRDY >> and RDR. > > we will only get RDR if message_size % threshold > 0. If we have a 16 > byte transfer and we program threshold to 8 bytes, we will get two RRDY > IRQs. > >> Felipe, do you have in mind why do you want to avoid RDR and XDR events? >> Something about errata? > > nothing about errata. As the commit log say (or tried to say), if the > entire message fits into the FIFO we save one interrupt. It's a > micro-optimization. I see, thank you. But due to error only half of fifo is utilized for that. And, I'll try to move fifo threshold init code into ISR. Don't see something wrong. Thank you a lot! Regards, Alexander. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
