The main reason is to avoid CON register access by omap_i2c_xfer_msg()
function, after transfer was submitted to IP.
Also changed NACK logic to wait ARDY so we can be sure what STP has
been sent on back to back transfers.
Tested on dm3730 (Beagleboard XM C).
Signed-off-by: Alexander Kochetkov <al.kochet@xxxxxxxxx>
---
drivers/i2c/busses/i2c-omap.c | 26 +++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 8591c0c..9e0d359 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -725,12 +725,9 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
return -EAGAIN;
if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
+ /* NOTE: IP always send stop on NACK */
if (msg->flags & I2C_M_IGNORE_NAK)
return 0;
-
- w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
- w |= OMAP_I2C_CON_STP;
- omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
return -EREMOTEIO;
}
return -EIO;
@@ -1022,8 +1019,24 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
}
if (stat & OMAP_I2C_STAT_NACK) {
- err |= OMAP_I2C_STAT_NACK;
+ u16 con;
+
+ dev->cmd_err |= OMAP_I2C_STAT_NACK;
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
+
+ /*
+ * According to the TRM, IP *always* send STP and reset
+ * MST in NACK cases. But for NACK in the middle of
+ * transfer IP doesn't do it. So, here is workaround.
+ */
+ con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
+ if (con & OMAP_I2C_CON_MST) {
+ con |= OMAP_I2C_CON_STP;
+ omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, con);
+ }
+
+ /* Wait for ARDY */
+ continue;
}
if (stat & OMAP_I2C_STAT_AL) {
@@ -1038,8 +1051,7 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
if (stat & OMAP_I2C_STAT_ARDY)
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ARDY);
- if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
- OMAP_I2C_STAT_AL)) {
+ if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_AL)) {
/*
* These are pending events not handled in time
* due to ISR latency.
--
1.7.9.5
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