Although RESET state of LIMITEDADDRESS bit in GPMC_CONFIG register
is 0 (i.e. A26-A11 enabled), faulty bootloaders might accidentally
set this bit. e.g. u-boot 2014.07 with CONFIG_NOR disabled.
Explicity disable LIMITEDADDRESS bit for non NAND devices so that
they can always work.
Signed-off-by: Roger Quadros <rogerq@xxxxxx>
Signed-off-by: Sekhar Nori <nsekhar@xxxxxx>
---
arch/arm/mach-omap2/gpmc.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index f5d9dd2..0ba95d3 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -85,6 +85,8 @@
#define GPMC_ECC_CTRL_ECCREG8 0x008
#define GPMC_ECC_CTRL_ECCREG9 0x009
+#define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
+
#define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
#define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
#define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
@@ -1501,6 +1503,7 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
struct resource res;
unsigned long base;
int ret, cs;
+ u32 val;
if (of_property_read_u32(child, "reg", &cs) < 0) {
dev_err(&pdev->dev, "%s has no 'reg' property\n",
@@ -1569,6 +1572,11 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
goto err;
}
+ /* Clear limited address i.e. enable A26-A11 */
+ val = gpmc_read_reg(GPMC_CONFIG);
+ val &= ~GPMC_CONFIG_LIMITEDADDRESS;
+ gpmc_write_reg(GPMC_CONFIG, val);
+
no_timings:
if (of_platform_device_create(child, NULL, &pdev->dev))
return 0;
--
1.8.3.2
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