Hi Roger,
On Tuesday 02 September 2014 07:27 PM, Roger Quadros wrote:
NAND uses wait pin only to indicate device readiness after
a block/page operation. It is not use to extend individual
read/write cycle and so read/write wait pin monitoring must
be disabled for NAND.
I think this is incorrect assumption. NAND framework allows
wait-pin monitoring at end of each read/write cycle. Please
refer following code in drivers/mtd/nand/nand_base.c
@@ void nand_wait_ready(...)
- nand_wait_ready() calls controller-driver specific call-back
for chip->dev_ready().
- chip->dev_ready in-case of OMAP NAND drivers is set in
drivers/mtd/nand/omap2.c during probe.
if (pdata->dev_ready) {
nand_chip->dev_ready = omap_dev_ready;
nand_chip->chip_delay = 0;
}
Problem is we don't set pdata->dev_ready correctly as part
of platform-data dring GPMC initialization. This was what my
earlier patch for wait-pin monitoring about. But it was a
quick fix for NAND devices.
So, I suggest to fix wait-pin monitoring instead of de-scoping
it from DTS as wait-pin monitoring should boast the NAND
performance significantly.
(please see if you can find an old mail thread which had some
good feedbacks from Ezequiel and Javier about wait-pin monitoring).
[...]
This patch also gets rid of the below warning when NAND is
accessed for the first time.
omap_l3_noc 44000000.ocp: L3 application error: target 13 mod:1 (unclearable)
Can you debug this further.
This warning probably comes when driver tries to access some
"reserved" addresses. Or violate read/write bits.
with regards, pekon
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