On Tue, 17 Jun 2014, Tero Kristo wrote: > On 06/17/2014 11:19 AM, Paul Walmsley wrote: > > > The only case that approached this was with PLLs. PLLs would > > automatically be placed into bypass if the PLL rate was set to the bypass > > rate. > > Someone could argue that this is rather strange approach also and would be > better to use some other API for the purpose. Probably so. clk_set_parent() doesn't fit very well, since the parent is exactly the same. Ideally there'd be some other API, like clk_lock_loop() and clk_unlock_loop(), given the sheer number of clock sources with optional, active loop compensation. Returning to the specific OMAP PLL case. When it was written there was some serious thought put into trying to determine how reasonable or safe of a thing it was to do. At the time, it was concluded that the bypass rates were unlikely to be configured by accident, since they were so low. Furthermore no one identified any negative effect of switching to the the bypass clock for the PLLs where it was practical (DPLL1, DPLL2). In fact it was considered a feature... - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
