Currently INTC interrupts are handled using handle_level_irq which
will acknowledge the interrupt before running the handler. If a second
interrupt is then asserted and this interrupt is disabled while
running the first handler, the INTC will be brought into an
inconsistent state. In this state the INTC will interrupt the CPU but
the interrupt pending registers will show no pending interrupts
causing the CPU to take no action. This will repeat until another
higher priority interrupt triggers, hogging the CPU.
handle_fasteoi_irq does not acknowledge the interrupt before after
running the handler, so using this for handling INTC interrupts avoid
the above problem. This also brings the handling more in line with the
sequence described in the TRM.
Signed-off-by: Stefan Sørensen <stefan.sorensen@xxxxxxxxxxxxxxx>
---
arch/arm/mach-omap2/irq.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index e022a86..9d09914 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -97,12 +97,6 @@ static void omap_ack_irq(struct irq_data *d)
intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
}
-static void omap_mask_ack_irq(struct irq_data *d)
-{
- irq_gc_mask_disable_reg(d);
- omap_ack_irq(d);
-}
-
static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
{
unsigned long tmp;
@@ -145,9 +139,9 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
struct irq_chip_type *ct;
gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
- handle_level_irq);
+ handle_fasteoi_irq);
ct = gc->chip_types;
- ct->chip.irq_ack = omap_mask_ack_irq;
+ ct->chip.irq_eoi = omap_ack_irq;
ct->chip.irq_mask = irq_gc_mask_disable_reg;
ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
--
1.8.5.3
--
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