On Wed, Jan 28, 2009 at 12:08:26PM -0700, Paul Walmsley wrote: > This patch causes a DPLL to enter bypass when it is instructed to set > its rate to that of its bypass clock. Previously this was only possible > after setting the DPLL rate, then disabling and re-enabling it. The more I think about this, especially with reference to patch D1, the more I'm convinced this is not entirely the right approach. Patch D1 introduces the necessary mechanics to make clk_get_parent() work. If you use this on a PLL clock, and the PLL is in bypass mode, it returns the non-bypass clock. Now, I suspect that your first thought to resolving that would be to add some complexity to clk_get_parent(). I advise against that. Instead, arrange for clk->parent to _always_ point at the correct parent clock, whether the PLL is in bypass mode or not. In other words, encapsulate all the PLL mechanics localized inside the PLL handling code and don't let them leak outside that code. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
