Hi Javier, (CCing Brian: What do you think about this?) On Thu, Dec 05, 2013 at 06:39:10PM +0100, Javier Martinez Canillas wrote: > On Thu, Dec 5, 2013 at 6:13 PM, Tony Lindgren <tony@xxxxxxxxxxx> wrote: > > In the another thread [0] pointed out by Enric we were discussing the > same issue. Thomas suggested [1] that ideally we should be able to set > a per MTD partition ECC scheme. That way we can set 1 bit hamming for > the first MTD partition that has the SPL that the boot ROM needs to > read and the other partitions can use a more secure ECC scheme. I > completely agree with him. > [..] > global ECC scheme and we should expand the GPMC NAND DT binding so > partitions support the "ti,nand-ecc-opt". I'll see if I can get some > free time to try to implement that. > AFAIK, there's no hardware limitation that would prevent us from setting a per-partition ECC, keep in mind this effort is not reduced to make devicetree accept ECC on the partitions. While there are some per MTD device (which model each partition), the ECC mode is present in the, nand_chip structure. My understanding is that the NAND core hasn't been designed for this use case, and thus some major re-work is needed to accomplish it. Therefore, it's a much short-term solution to implement the OMAP module parameter to fix the issue. Of course, feel free to prove me wrong :-) -- Ezequiel García, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
