a quick followup on this: On Thu, 11 Dec 2008, Paul Walmsley wrote: > With voltage change: > MPU @ 83MHz: 130 ticks (3.97 ms) worst-case It recently occurred to me that part of this 130 tick time is due to the udelay()s in the SmartReflex code. My test code did not update loops_per_jiffy when it did the MPU rate, so the udelay()s there would loop for longer than they should. So that needs to be fixed and re-measured. Presumably further improvements would be gained by converting sr_voltagescale_vcbypass() to be interrupt-driven, rather than polling for the voltage change to complete. That should reduce the CORE DVFS time further. - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
