Re: McBSP register question

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On Sun, Dec 14, 2008 at 9:38 PM, shekhar, chandra <x0044955@xxxxxx> wrote:
> ----- Original Message ----- From: "Jason Marini" <jason.marini@xxxxxxxxx>
> To: <linux-omap@xxxxxxxxxxxxxxx>
> Sent: Friday, December 12, 2008 11:51 PM
> Subject: McBSP register question
>
>
>> Looking at the latest git head, I see that omap_mcbsp_pollwrite() and
>> omap_mcbsp_pollread() improperly use readw() and writew() instead of
>> OMAP_MCBSP_READ() and OMAP_MCBSP_WRITE() in the file
>> arch/arm/plat-omap/mcbsp.c.
>>
>> But while I was editing this file, I also saw writes to
>> OMAP_MCBSP_REG_DXR1, which is #define'd for ARCH_OMAP_34XX and
>> ARCH_OMAP_24XX to be at an offset of 0x0C.  The McBSP section of the
>> TRM for the OMAP34xx has no mention of any registers existing at this
>> offset.
>>
>> Why is this DXR1 and not just DXR?
>
> It so happens that McBSP on 2420 has DXR1 and DXR2 registers, but not on
> omap2430/34xx.
> To provide multi-omap suport and avoid ifdefs dxr1/2 and drr1/2 has been
> retained along with dxr and drr  (same code mach-omap2/mcbsp.c supports
> 2420.) .

I suspected as much - thank you for the response.

-Jason
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