Paul >-----Original Message----- >From: linux-omap-owner@xxxxxxxxxxxxxxx [mailto:linux-omap-owner@xxxxxxxxxxxxxxx] On Behalf Of Paul >Walmsley >Sent: Thursday, December 11, 2008 3:23 PM >To: linux-omap@xxxxxxxxxxxxxxx >Subject: [PATCH 2/3] OMAP3 EHCI: use clock framework to program DPLL5, DPLL5_M2_CLK > >For testing only, not for merging. > >Use the clock framework to program DPLL5, DPLL5_M2_CLK. >--- > drivers/usb/host/ehci-omap.c | 57 +++++++++++++++++++++++++++--------------- > 1 files changed, 36 insertions(+), 21 deletions(-) > >diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c >index 5252e75..2057f58 100644 >--- a/drivers/usb/host/ehci-omap.c >+++ b/drivers/usb/host/ehci-omap.c >@@ -70,6 +70,8 @@ struct ehci_omap_clock_defs { > struct clk *usbhost1_48m_fck_clk; > struct clk *usbtll_fck_clk; > struct clk *usbtll_ick_clk; >+ struct clk *dpll5_clk; >+ struct clk *dpll5_m2_clk; > }; Can we have these clocks hidden from the driver. USB-Host understands only : 2 fclocks 1 iclock The DPLL5 is outside the USBHOST module in the DPLL5 part. Ideally, the clock node for say USBHOST-iclock should internally enable all the parent clocks. > > /* Clock names as per clock framework: May change so keep as #defs */ >@@ -163,28 +165,29 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd) > ((char *)hcd_to_ehci(hcd)) + > sizeof(struct ehci_hcd)); > >- /* Start DPLL5 Programming: >- * Clock Framework is not doing this now: >- * This will be done in clock framework later >+ /* >+ * Make sure DPLL5 is programmed for 120MHz >+ * XXX should be done at DPLL init time >+ * XXX dpll rates should be assigned to clk->rate at init time >+ * XXX enable DPLL autoidle > */ >- /* Enable DPLL 5 : Based on Input of 13Mhz*/ >- cm_write_mod_reg((12 << OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT)| >- (120 << OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT), >- PLL_MOD, OMAP3430ES2_CM_CLKSEL4); >- >- cm_write_mod_reg(1 << OMAP3430ES2_DIV_120M_SHIFT, >- PLL_MOD, OMAP3430ES2_CM_CLKSEL5); >- >- cm_write_mod_reg((7 << OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT) | >- (7 << OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT), >- PLL_MOD, OMAP3430ES2_CM_CLKEN2); >- >- while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST2) & >- OMAP3430ES2_ST_PERIPH2_CLK_MASK)) >- dev_dbg(hcd->self.controller, >- "idlest2 = 0x%x\n", >- cm_read_mod_reg(PLL_MOD, CM_IDLEST2)); >- /* End DPLL5 programming */ >+ ehci_clocks->dpll5_clk = clk_get(&dev->dev, "dpll5_ck"); >+ if (IS_ERR(ehci_clocks->dpll5_clk)) { >+ WARN_ON(1); >+ return PTR_ERR(ehci_clocks->dpll5_clk); >+ }; >+ if (clk_get_rate(ehci_clocks->dpll5_clk) != 120000000) >+ clk_set_rate(ehci_clocks->dpll5_clk, 120000000); >+ clk_enable(ehci_clocks->dpll5_clk); >+ >+ /* Program dpll5_m2_clk divider for no division */ >+ ehci_clocks->dpll5_m2_clk = clk_get(&dev->dev, "dpll5_m2_ck"); >+ if (IS_ERR(ehci_clocks->dpll5_m2_clk)) { >+ WARN_ON(1); >+ return PTR_ERR(ehci_clocks->dpll5_m2_clk); >+ }; >+ clk_enable(ehci_clocks->dpll5_m2_clk); >+ clk_set_rate(ehci_clocks->dpll5_m2_clk, 120000000); > > /* Enable Clocks for USBHOST */ > ehci_clocks->usbhost_ick_clk = clk_get(&dev->dev, >@@ -375,6 +378,18 @@ static void omap_stop_ehc(struct platform_device *dev, struct usb_hcd *hcd) > ehci_clocks->usbtll_ick_clk = NULL; > } > >+ if (ehci_clocks->dpll5_m2_clk != NULL) { >+ clk_disable(ehci_clocks->dpll5_m2_clk); >+ clk_put(ehci_clocks->dpll5_m2_clk); >+ ehci_clocks->dpll5_m2_clk = NULL; >+ } >+ >+ if (ehci_clocks->dpll5_clk != NULL) { >+ clk_disable(ehci_clocks->dpll5_clk); >+ clk_put(ehci_clocks->dpll5_clk); >+ ehci_clocks->dpll5_clk = NULL; >+ } >+ > > #ifdef EXTERNAL_PHY_RESET > gpio_free(EXT_PHY_RESET_GPIO_PORT1); > > >-- >To unsubscribe from this list: send the line "unsubscribe linux-omap" in >the body of a message to majordomo@xxxxxxxxxxxxxxx >More majordomo info at http://vger.kernel.org/majordomo-info.html ��.n��������+%������w��{.n�����{�������ܨ}���Ơz�j:+v�����w����ޙ��&�)ߡ�a����z�ޗ���ݢj��w�f
