----- Original Message -----
From: <ext-eero.nurkkala@xxxxxxxxx>
To: <linux-omap@xxxxxxxxxxxxxxx>
Cc: "Eero Nurkkala" <ext-eero.nurkkala@xxxxxxxxx>
Sent: Tuesday, November 11, 2008 12:22 PM
Subject: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers
From: Eero Nurkkala <ext-eero.nurkkala@xxxxxxxxx>
The prescalers for 100 kHz and 400 kHz mode
are wrong. The internal clock is the fclock
divided by the prescaler. Also, the scll and
sclh values should be adjusted correctly.
Having the correct prescaler is important in
the process of getting standard i2c clock. In
addition, it (psc) is used to get the correct
noise filter and thus, lets more error resilient
i2c communications.
Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@xxxxxxxxx>
---
drivers/i2c/busses/i2c-omap.c | 12 +++++++++---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index f15668d..cee2f2d 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -288,7 +288,13 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
if (cpu_is_omap2430() || cpu_is_omap34xx()) {
/* HSI2C controller internal clk rate should be 19.2 Mhz */
- internal_clk = 19200;
+ if (dev->speed > 400)
+ internal_clk = 19200;
+ else if (dev->speed > 100)
+ internal_clk = 9600;
+ else
+ internal_clk = 4000;
Is internal clk 4000 valid?? PSC_REG field cannot encompass ( its 4 bit field)
the calculated psc if internal_clk is 4000.
+
fclk_rate = clk_get_rate(dev->fclk) / 1000;
/* Compute prescaler divisor */
@@ -306,8 +312,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
hssclh = fclk_rate / (dev->speed * 2) - 6;
} else {
/* To handle F/S modes */
- fsscll = internal_clk / (dev->speed * 2) - 6;
- fssclh = internal_clk / (dev->speed * 2) - 6;
+ fsscll = internal_clk / (dev->speed * 2) - 7;
+ fssclh = internal_clk / (dev->speed * 2) - 5;
}
scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
--
1.6.0
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