FSUSB Register access

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Hello,

I am using Montavista Mobilinux 5 on OMAP2430 and I am trying to access
the FSUSB register set and the kernel halts upon any attempt to access
any of the registers in the FSUSB.

Note, under the Mobilinux distribution, the HSUSB controller is used by
default, not the FSUSB controller.  I am trying to access both so that I
can have USB port 0 controlled by the HSUSB and port 1 controlled by the
FSUSB controller.

Per the TI spec, the host and device register sets within the FSUSB
controller can only be accessed if the OTG register set is correctly
configured.  However, the OTG register set should be accessible as long
as there is a 48MHz clock.

I have tried reading the OTG_REVISION register (0x4805e300) and the
OTG_SYSCON_1_REG (0x4805e304) within arch/arm/plat-omap/usb.c. Upon
either read, the kernel halts and I do not see any logs at startup after
the 
"Uncompressing
Linux.............................................................
........................................... done, booting the kernel."
message.

If I comment out the register accesses, I do see the startup log and I
see the following log statements within arch/arm/plat-omap/usb.c
"Timeout enabling clock usb_l4_ick" 
"Timeout enabling clock usb_fck" 

In addition I have printed out various register values and they are as
follows.

Various register values:

CM_FCLKEN2_CORE - Address:0x49006204 - value 0x001B07BF,bit 0 is 0x1,
should be 1

CM_ICLKEN2_CORE - Address:0x49006214 - value 0x00000FFF,bit 0 is 0x1,
should be 1

CM_IDLEST2_CORE - Address:0x49006224 - value 0x00000FFE,bit 0 is 0x0,
should be 1  --- Possibly this is causing my problem but it is not clear
to me what I need to do to have this set to a '1'.

CM_AUTOIDLE2_CORE - Address:0x49006234 - value 0x00000000,bit 0 is 0x0,
should be 0

CM_CLKSEL1_CORE - Address:0x49006240 - value 0x02102946,bits 27-25 is
0x1, should be 1 for L3_CLK/1 (boot mode only), 2 for L3_CLK/2, or 4 for
L3_CLK/4

PM_WKEN2_CORE - Address:0x490062A4 - value 0x00000000,bit 0 is 0x0,
should be 0 for disabled, 1 for enabled  -- Per TI, this does not need
to be enabled...

PM_WKST2_CORE - Address:0x490062B4 - value 0x00000000,bit 0 is 0x0,
should be 0 for not occurred, 1 for occurred

CM_IDLEST_CKGEN - Address:0x49006520 - value 0x00000336,bit 4 is 0x1,
should be 0x1 for active 48M_CLK


Any ideas as to what the register settings need to be to enable access
to the FSUSB OTG registers?

Thanks,
Jeff



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