> From: David Brownell [mailto:david-b@xxxxxxxxxxx] > Sent: Saturday, November 01, 2008 1:09 AM > > For the next series of ARMv7 Cortex's this is all being projected > > to require much more strictness in access ordering and use of barriers. > > Any particular kind of barriers? barrier() is compiler advice, > and gets the most use in Linux ... but <asm/system.h> reminds > me that V7 has isb/dsb/dmb instructions, and V6 can do them too. > (Now I'll have to go look at what they do again...) > > That case needed a dsb analogue (on armv5, flush write buffer). In doc's and training material there are examples of sequences which need care. As they are not our doc's I can't publicly share them. They will start showing up over time as hardware becomes more real. Single core is more aggressive and the dual core variants compound issues. >From a given CPU's point of few it is free to do many things to normal memory behind your back as long at the time you access it (from a single CPU point of view) the value is correct. This requires strict care to be 100% safe in coordinating with DMA to normal memories. For A8 today many aspects of this are less relevant as implementation won't do it all yet. Regards, Richard W. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
