> owner@xxxxxxxxxxxxxxx] On Behalf Of David Brownell > Sent: Friday, October 31, 2008 4:59 PM > As in, issue those dma cache updates, then write to the > DMA or peripheral controller registers ... and the key data > was still in the write buffers when those writes completed! > That's quite unusual; possibly related to memory controller > bugs in that silicon revision. For the next series of ARMv7 Cortex's this is all being projected to require much more strictness in access ordering and use of barriers. There have been some cautions about newer write buffer policies which try and keep data instead of flushing it. Today even if you miss some drain in a small amount of time it will happen. That may not be the case always. Regards, Richard W. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
