On Monday 08 September 2008, Kamat, Nishant wrote: > +config MTD_NAND_OMAP_PREFETCH > + bool "GPMC prefetch support for NAND Flash device" > + depends on MTD_NAND && MTD_NAND_OMAP2 > + default n > + help > + The NAND device can be accessed for Read/Write using GPMC PREFETCH engine > + to improve the performance. Is there a reason this isn't always enabled, and the choice is just whether to use DMA or not? I'd be interested to see performance measurements for the three cases. - current/slow code - the readsw() update I sent previously - this "prefetch engine" And I'd expect this "prefetch engine" code would also be improved by using readsw() and writesw() when DMA isn't in use. On one ARM926 I observed a 16% speedup *just* from switching from slow byte-at-a-time PIO to using readsb ... this current code has that same pessimization. - Dave > + > +choice > + prompt "Prefetch engine support for GPMC" > + depends on MTD_NAND_OMAP_PREFETCH > + help > + The GPMC PREFETCH engine can be configured eigther in MPU interrupt mode > + or in DMA interrupt mode. > + > +config MTD_NAND_OMAP_PREFETCH_MPU > + depends on MTD_NAND_OMAP_PREFETCH > + bool "MPU mode always for spare area + MPU mode for main area" > + help > + Say y if... you want MPU interrupt mode for both spare area and main area accesses. > + > +config MTD_NAND_OMAP_PREFETCH_DMA > + depends on MTD_NAND_OMAP_PREFETCH > + bool "MPU mode always for spare area + DMA mode for main area" > + help > + Say y if... you want MPU interrupt mode for spare area and DMA mode for main > + area access. > + > +endchoice > + -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
