Hello, A quick update on the CORE DPLL M2 divider change patches; they seem to work okay on the BeagleBoard here. (The rate tables need minor tweaks to match the Beagle DPLL clock rates set up by u-boot.) Not sure what's going on with the 3430SDP. I suspect there are some PRCM register contents that are not being properly reset during the FPGA-driven warm reboots used here. - Paul root@(none):~# mount -t debugfs none /mnt root@(none):~# cd /mnt/clock/virt_26m_ck/osc_sys_ck/sys_ck/dpll3_ck/dpll3_m2_ck root@(none):/mnt/clock/virt_26m_ck/osc_sys_ck/sys_ck/dpll3_ck/dpll3_m2_ck# echo -n 166000000 > rate clock: clksel_round_rate_div: dpll3_m2_ck target_rate 166000000 clock: new_div = 2, new_rate = 166000000 clock: changing CORE DPLL rate from 332000000 to 166000000 clock: current SDRC timing params: 0004dc01 aa9db4c6 00011517 clock: new SDRC timing params: 00025501 51512283 0001120c clk: clk_set_rate(dpll3_m2_ck, 166000000) returns 0 root@(none):/mnt/clock/virt_26m_ck/osc_sys_ck/sys_ck/dpll3_ck/dpll3_m2_ck# echo -n 332000000 > rate clock: clksel_round_rate_div: dpll3_m2_ck target_rate 332000000 clock: new_div = 1, new_rate = 332000000 clock: changing CORE DPLL rate from 166000000 to 332000000 clock: current SDRC timing params: 00025501 51512283 0001120c clock: new SDRC timing params: 0004dc01 9a9db4c6 00011217 clk: clk_set_rate(dpll3_m2_ck, 332000000) returns 0 root@(none):/mnt/clock/virt_26m_ck/osc_sys_ck/sys_ck/dpll3_ck/dpll3_m2_ck# -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
