> -----Original Message----- > From: Paul Walmsley [mailto:paul@xxxxxxxxx] > Sent: Wednesday, July 09, 2008 5:17 AM > To: Woodruff, Richard > Cc: Nayak, Rajendra; linux-omap@xxxxxxxxxxxxxxx; 'Igor Stoppa' > Subject: RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 > divider, clean up SDRC > > On Tue, 8 Jul 2008, Woodruff, Richard wrote: > > > > > SRAM being mapped as cacheable could be a possible > reason for this. > > > > Second this. > > Yeah, agreed that it needs to be done, but SRAM in CDP 12.17 is still > marked cacheable too, right? Did CORE M2 divider changes work in CDP > 12.17? > > Also still curious why, if it's the cache line eviction > issue, it only > locks up on the low- to high-speed transition. While we saw the issues due to cache line eviction, I remember it used to pop up both during a low-to-high and high-to-low transitions. If you are seeing this only during a low-to-high, it probably could be something else. > > > Can you ping the board by chance when you are locked? Is only user > > space locked out or is the board dead. The SRAM thing > resulted in a dead > > lock where MPU was done. > > The board doesn't respond to pings. > > > - Paul > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
