This workaround is needed because we don't have smartreflex
driver. These configurations are taken from TI's reference code.
Signed-off-by: Jouni Hogander <jouni.hogander@xxxxxxxxx>
---
arch/arm/mach-omap2/pm34xx.c | 74 ++++++++++++++++++++++++++++++++++++++
drivers/i2c/chips/twl4030-core.c | 9 +++++
2 files changed, 83 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index be3c74f..1476597 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -357,6 +357,25 @@ static struct platform_suspend_ops omap_pm_ops = {
.valid = suspend_valid_only_mem,
};
+/* PRM_VC_CMD_VAL_0 specific bits */
+#define PRM_VC_CMD_VAL0_ON 0x30
+#define PRM_VC_CMD_VAL0_ONLP 0x18
+#define PRM_VC_CMD_VAL0_RET 0x18
+#define PRM_VC_CMD_VAL0_OFF 0x18
+
+/* PRM_VC_CMD_VAL_1 specific bits */
+#define PRM_VC_CMD_VAL1_ON 0x2C
+#define PRM_VC_CMD_VAL1_ONLP 0x18
+#define PRM_VC_CMD_VAL1_RET 0x18
+#define PRM_VC_CMD_VAL1_OFF 0x18
+
+/* PRM_VOLTCTRL */
+#define PRM_VOLTCTRL_AUTO_RET 0x2
+
+/* T2 SMART REFLEX */
+#define R_SRI2C_SLAVE_ADDR 0x12
+#define R_VDD1_SR_CONTROL 0x00
+#define R_VDD2_SR_CONTROL 0x01
static void __init prcm_setup_regs(void)
{
/* setup wakup source */
@@ -369,6 +388,61 @@ static void __init prcm_setup_regs(void)
* it is selected to mpu wakeup goup */
prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
+
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ /* XXX These are smartreflex related and are here as long as we
+ * have working smartreflex driver in linux-omap tree */
+ prm_write_mod_reg((R_SRI2C_SLAVE_ADDR <<
+ OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT) |
+ (R_SRI2C_SLAVE_ADDR <<
+ OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT),
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_SMPS_SA_OFFSET);
+
+ prm_write_mod_reg((R_VDD2_SR_CONTROL <<
+ OMAP3430_VOLRA1_SHIFT) |
+ (R_VDD1_SR_CONTROL <<
+ OMAP3430_VOLRA0_SHIFT),
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
+
+ prm_write_mod_reg((PRM_VC_CMD_VAL0_ON <<
+ OMAP3430_VC_CMD_ON_SHIFT) |
+ (PRM_VC_CMD_VAL0_ONLP <<
+ OMAP3430_VC_CMD_ONLP_SHIFT) |
+ (PRM_VC_CMD_VAL0_RET <<
+ OMAP3430_VC_CMD_RET_SHIFT) |
+ (PRM_VC_CMD_VAL0_OFF <<
+ OMAP3430_VC_CMD_OFF_SHIFT),
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
+
+ prm_write_mod_reg((PRM_VC_CMD_VAL1_ON <<
+ OMAP3430_VC_CMD_ON_SHIFT) |
+ (PRM_VC_CMD_VAL1_ONLP <<
+ OMAP3430_VC_CMD_ONLP_SHIFT) |
+ (PRM_VC_CMD_VAL1_RET <<
+ OMAP3430_VC_CMD_RET_SHIFT) |
+ (PRM_VC_CMD_VAL1_OFF <<
+ OMAP3430_VC_CMD_OFF_SHIFT),
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_CMD1 |
+ OMAP3430_RAV1,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_CH_CONF_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_MCODE_SHIFT |
+ OMAP3430_HSEN |
+ OMAP3430_SREN,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_I2C_CFG_OFFSET);
+
+ prm_write_mod_reg(PRM_VOLTCTRL_AUTO_RET,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VOLTCTRL_OFFSET);
+ }
}
static int __init pwrdms_setup(struct powerdomain *pwrdm)
diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
index 8822653..96e6216 100644
--- a/drivers/i2c/chips/twl4030-core.c
+++ b/drivers/i2c/chips/twl4030-core.c
@@ -119,6 +119,7 @@
/* Few power values */
#define R_CFG_BOOT 0x05
#define R_PROTECT_KEY 0x0E
+#define R_DCDC_GLOBAL_CFG 0x06
/* access control */
#define KEY_UNLOCK1 0xce
@@ -709,6 +710,14 @@ static int power_companion_init(void)
e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, ctrl, R_CFG_BOOT);
e |= protect_pm_master();
+ /* XXX Enable smart reflex. Voltage scaling method should be
+ * passed in platform data */
+ e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER,
+ &ctrl, R_DCDC_GLOBAL_CFG);
+ ctrl |= 0x8;
+ e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+ ctrl, R_DCDC_GLOBAL_CFG);
+
return e;
}
--
1.5.5
--
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