Adding TI pm files for clock framework
Signed-off-by: Karthik Dasu <karthik-dp@xxxxxx>
Acked-by: Richard Woodruff <r-woodruff2@xxxxxx>
Acked-by: Vikram Pandita <vikram.pandita@xxxxxx>
---
arch/arm/mach-omap2/clock_34xx.c | 934 +++++++++++++++++++++++
arch/arm/mach-omap2/clock_34xx.h | 1529 ++++++++++++++++++++++++++++++++++++++
include/asm-arm/arch-omap/clock.h | 3
3 files changed, 2466 insertions(+)
Index: git-latest5/arch/arm/mach-omap2/clock_34xx.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ git-latest5/arch/arm/mach-omap2/clock_34xx.c 2008-02-29 20:29:47.055287953 +0530
@@ -0,0 +1,927 @@
+/*
+ * linux/arch/arm/mach-omap2/clock_34xx.c
+ *
+ * OMAP34XX clock framework
+ *
+ * Copyright (C) 2007 Texas Instruments Inc.
+ * Karthik Dasu <karthik-dp@xxxxxx>
+ *
+ * Based on omap2 clock.c Copyright (C) 2005 Texas Instruments Inc
+ * Richard Woodruff <r-woodruff2@xxxxxx>
+ * Cleaned up and modified to use omap shared clock framework by
+ * Tony Lindgren <tony@xxxxxxxxxxx>
+ *
+ * Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen@xxxxxxxxxxxxxx>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sram.h>
+
+#include "prcm-regs.h"
+#include "memory.h"
+#include "clock_34xx.h"
+
+#ifdef CONFIG_OMAP34XX_OFFMODE
+#define TIMER_PENDING 1
+#define TIMER_EXPIRED 0
+
+#include <linux/timer.h>
+
+static spinlock_t inatimer_lock;
+
+struct timer_list coredomain_timer;
+struct timer_list perdomain_timer;
+
+struct inactivity_timer{
+ u32 start_time, value;
+ u32 module_timeout_value[32];
+ struct timer_list *off_timer;
+};
+
+static struct inactivity_timer domain_inatimer[2];
+
+void modify_timeout_value(struct clk *clk, u32 value)
+{
+ u32 prcm_id, domain_id, device_id;
+ struct inactivity_timer *inatimer;
+
+#ifdef CONFIG_TRACK_RESOURCES
+ struct resource_handle *res = (struct resource_handle *) clk;
+ prcm_id = res->clk->prcmid;
+#else
+ prcm_id = clk->prcmid;
+#endif
+ domain_id = DOMAIN_ID(prcm_id);
+ device_id = DEV_BIT_POS(prcm_id);
+
+ if (domain_id == DOM_CORE1) {
+ inatimer = &domain_inatimer[0];
+ } else if (domain_id == DOM_PER) {
+ inatimer = &domain_inatimer[1];
+ } else {
+ printk(KERN_WARNING "Inactivity timer not supported\n");
+ return;
+ }
+ inatimer->module_timeout_value[device_id] = value;
+}
+EXPORT_SYMBOL(modify_timeout_value);
+
+void modify_inatimer(struct clk *clk)
+{
+ u32 prcm_id, domain_id, device_id;
+ u32 new_value, remaining_time;
+ struct inactivity_timer *inatimer;
+
+#ifdef CONFIG_TRACK_RESOURCES
+ struct resource_handle *res = (struct resource_handle *) clk;
+ prcm_id = res->clk->prcmid;
+#else
+ prcm_id = clk->prcmid;
+#endif
+ domain_id = DOMAIN_ID(prcm_id);
+ device_id = DEV_BIT_POS(prcm_id);
+
+ spin_lock(&inatimer_lock);
+ if (domain_id == DOM_CORE1) {
+ inatimer = &domain_inatimer[0];
+ inatimer->off_timer = &coredomain_timer;
+ } else if (domain_id == DOM_PER) {
+ inatimer = &domain_inatimer[1];
+ inatimer->off_timer = &perdomain_timer;
+ } else {
+ printk(KERN_WARNING "Inactivity timer not supported\n");
+ spin_unlock(&inatimer_lock);
+ return;
+ }
+
+ new_value = inatimer->module_timeout_value[device_id];
+
+ if (new_value != 0) {
+ /* If timer pending, check the remaining time and restart
+ * the timer if required
+ */
+ if (timer_pending(inatimer->off_timer)) {
+ remaining_time = inatimer->value -
+ (((jiffies - inatimer->start_time) * 1000) / HZ);
+
+ if (new_value > remaining_time) {
+ mod_timer(inatimer->off_timer, jiffies +
+ (new_value * HZ / 1000));
+ inatimer->start_time = jiffies;
+ inatimer->value = new_value;
+ }
+ } else {
+
+ mod_timer(inatimer->off_timer, jiffies +
+ (new_value * HZ / 1000));
+ inatimer->start_time = jiffies;
+ inatimer->value = new_value;
+ }
+ }
+ spin_unlock(&inatimer_lock);
+
+}
+
+int coredomain_timer_pending(void)
+{
+ int ret;
+
+ if (timer_pending(&coredomain_timer))
+ ret = TIMER_PENDING;
+ else
+ ret = TIMER_EXPIRED;
+
+ return ret;
+}
+EXPORT_SYMBOL(coredomain_timer_pending);
+
+static void coredomain_timer_func(unsigned long data)
+{
+ /* CORE domain timer function */
+}
+
+int perdomain_timer_pending(void)
+{
+ int ret;
+
+ if (timer_pending(&perdomain_timer))
+ ret = TIMER_PENDING;
+ else
+ ret = TIMER_EXPIRED;
+
+ return ret;
+}
+EXPORT_SYMBOL(perdomain_timer_pending);
+
+static void perdomain_timer_func(unsigned long data)
+{
+ /* PER domain timer function */
+}
+#endif /* #ifdef CONFIG_OMAP34XX_OFFMODE */
+
+static struct vdd_prcm_config *curr_vdd1_prcm_set;
+static struct vdd_prcm_config *curr_vdd2_prcm_set;
+
+static unsigned long compute_lpj(unsigned long ref, u_int div, u_int mult)
+{
+ unsigned long new_jiffy_l, new_jiffy_h;
+
+ /*
+ * Recalculate loops_per_jiffy. We do it this way to
+ * avoid math overflow on 32-bit machines. Maybe we
+ * should make this architecture dependent? If you have
+ * a better way of doing this, please replace!
+ *
+ * new = old * mult / div
+ */
+ new_jiffy_h = ref / div;
+ new_jiffy_l = (ref % div) / 100;
+ new_jiffy_h *= mult;
+ new_jiffy_l = new_jiffy_l * mult / div;
+
+ return new_jiffy_h + new_jiffy_l * 100;
+}
+
+/*-------------------------------------------------------------------------
+ * Omap3 specific clock functions
+ *-------------------------------------------------------------------------*/
+/* Make the rate same as that of the parent.
+ If the rate propagates, call propagate_rate*/
+static void omap3_followparent_recalc(struct clk *clk)
+{
+ followparent_recalc(clk);
+ if (clk->flags & RATE_PROPAGATES)
+ propagate_rate(clk);
+}
+
+static void omap3_propagate_rate(struct clk *clk)
+{
+ propagate_rate(clk);
+}
+
+/* Calls PRCM APIs to enable clock */
+static int _omap3_clk_enable(struct clk *clk)
+{
+#ifdef ENABLE_CLOCKCONTROL
+ int ret = 0;
+
+ pr_debug("Clk: %s\n", clk->name);
+ if (clk->flags & ALWAYS_ENABLED)
+ return 0;
+
+ if (clk == &sys_clkout1)
+ ret = prcm_control_external_output_clock1(PRCM_ENABLE);
+
+ if (clk == &sys_clkout2)
+ ret = prcm_control_external_output_clock2(PRCM_ENABLE);
+
+ if (clk->flags & F_CLK)
+ ret =
+ prcm_clock_control(clk->prcmid, FCLK, PRCM_ENABLE,
+ PRCM_ACCESS_CHK);
+ if (clk->flags & I_CLK)
+ ret =
+ prcm_clock_control(clk->prcmid, ICLK, PRCM_ENABLE,
+ PRCM_ACCESS_CHK);
+
+ pr_debug("Done Clk: %s\n", clk->name);
+ if (ret == PRCM_FAIL)
+ return -EINVAL;
+ else
+ return 0;
+#else
+ return 0;
+#endif
+}
+
+/* Calls PRCM APIs to disable clock */
+static void _omap3_clk_disable(struct clk *clk)
+{
+#ifdef ENABLE_CLOCKCONTROL
+ pr_debug("Clk: %s\n", clk->name);
+ if (clk->flags & ALWAYS_ENABLED)
+ return;
+
+ if (clk == &sys_clkout1)
+ prcm_control_external_output_clock1(PRCM_DISABLE);
+
+ if (clk == &sys_clkout2)
+ prcm_control_external_output_clock2(PRCM_DISABLE);
+
+ if (clk->flags & F_CLK)
+ prcm_clock_control(clk->prcmid, FCLK, PRCM_DISABLE,
+ PRCM_NO_ACCESS_CHK);
+
+ if (clk->flags & I_CLK)
+ prcm_clock_control(clk->prcmid, ICLK, PRCM_DISABLE,
+ PRCM_NO_ACCESS_CHK);
+
+ pr_debug("Done Clk: %s\n", clk->name);
+#endif
+}
+
+/* Update usecount and disable clock if usecount reaches 0 */
+static void omap3_clk_disable(struct clk *clk)
+{
+ pr_debug("Name %s\n", clk->name);
+ if (clk->usecount > 0 && !(--clk->usecount)) {
+ _omap3_clk_disable(clk);
+ if (likely((u32) clk->parent))
+ omap3_clk_disable(clk->parent);
+ }
+#ifdef CONFIG_OMAP34XX_OFFMODE
+ context_save_done(clk);
+#endif /* #ifdef CONFIG_OMAP34XX_OFFMODE */
+ pr_debug("usecount: %d,%s\n", clk->usecount, clk->name);
+}
+
+/* Enable clock if it is not already enabled and update usecount */
+static int omap3_clk_enable(struct clk *clk)
+{
+ int ret = 0;
+ pr_debug("Name %s\n", clk->name);
+ if (clk->usecount++ == 0) {
+ if (likely((u32) clk->parent))
+ ret = omap3_clk_enable(clk->parent);
+ if (unlikely(ret != 0)) {
+ clk->usecount--;
+ return ret;
+ }
+
+ ret = _omap3_clk_enable(clk);
+
+ if (unlikely(ret != 0) && clk->parent) {
+ omap3_clk_disable(clk->parent);
+ clk->usecount--;
+ }
+ }
+ pr_debug("usecount: %d,%s\n", clk->usecount, clk->name);
+ return ret;
+}
+
+/* Calls appropriate PRCM API to calculate rate of clock */
+static void omap3_clk_recalc(struct clk *clk)
+{
+ u32 parent_rate, divider, ret, rate;
+ parent_rate = clk->parent->rate;
+ ret = PRCM_PASS;
+
+ pr_debug("Clock name: %s\n", clk->name);
+
+ if (clk == &sys_ck) {
+ clk->rate = prcm_get_system_clock_speed() * 1000;
+ ret = PRCM_PASS;
+ }
+
+ if (clk == &mpu_ck) {
+ ret = prcm_get_processor_speed(clk->prcmid, &rate);
+ clk->rate = rate * 1000;
+ }
+
+ if (clk == &iva2_ck) {
+ ret = prcm_get_processor_speed(clk->prcmid, &rate);
+ clk->rate = rate * 1000;
+ }
+
+ if (clk->flags & DPLL_OUTPUT) {
+ ret = prcm_get_dpll_rate(clk->prcmid, &rate);
+ if (ret == PRCM_PASS)
+ clk->rate = rate * 1000;
+ }
+
+ if (clk->flags & RATE_CKCTL) {
+ ret = prcm_clksel_get_divider(clk->prcmid, ÷r);
+ pr_debug("Divider: %d\n", divider);
+ if (ret == PRCM_PASS)
+ clk->rate = clk->parent->rate / divider;
+ }
+
+ if (ret != PRCM_PASS)
+ printk(KERN_ERR "Error in clk_recalc: %d,%s\n", ret, clk->name);
+
+ pr_debug("Rate: %lu\n", clk->rate);
+
+ if (clk->flags & RATE_PROPAGATES)
+ propagate_rate(clk);
+}
+
+/* Given a clock and a rate apply a clock specific rounding function */
+/* This function should be called only for those clocks which have
+ * dividers and which are not part of a clock configuration. In case
+ * it is called for these clocks, it returns the current rate of the clocks */
+static long omap3_clk_round_rate(struct clk *tclk, unsigned long rate)
+{
+ u32 new_div = 0, mnoutput;
+ int ret;
+ int valid_rate, parent_rate;
+
+ pr_debug("Clock name: %s\n", tclk->name);
+
+ if (tclk->flags & RATE_FIXED)
+ return tclk->rate;
+
+ /* For external mcbsp clock node, rate is supposed to be set by
+ * the corresponding device driver. So round rate will return
+ * the rate that is supposed to be set */
+ if (tclk == &ext_mcbsp_ck)
+ return rate;
+ if ((tclk->flags & VDD1_CONFIG_PARTICIPANT)
+ || (tclk->flags & VDD2_CONFIG_PARTICIPANT))
+ /* If the clock is part of a clock configuration, it cannot
+ be changed on the fly */
+ return tclk->rate;
+
+ if (tclk->flags & DPLL_OUTPUT) {
+ /* The only clocks for which DPLL OUTPUT can be changed on
+ * the fly (by changing only MX dividers) are:
+ * PRCM_DPLL3_M3X2_CLK, PRCM_DPLL4_M2X2_CLK,
+ *PRCM_DPLL4_M3X2_CLK, PRCM_DPLL4_M4X2_CLK,
+ *PRCM_DPLL4_M5X2_CLK, PRCM_DPLL4_M6X2_CLK */
+ ret = prcm_get_dpll_mn_output(tclk->prcmid, &mnoutput);
+ /*mnoutput has CLKOUT = (Freq*m)/n+1 in case dpll is locked
+ *or bypass clock if it is not locked */
+ if (ret != PRCM_PASS)
+ /* Rate cannot be changed. Return original rate*/
+ return tclk->rate;
+ ret =
+ prcm_clksel_round_rate(tclk->prcmid, (2 * mnoutput),
+ (rate / 1000), &new_div);
+ if (ret == PRCM_PASS) {
+ valid_rate = (2 * mnoutput * 1000) / new_div;
+ pr_debug("Valid rate: %d\n", valid_rate);
+ return valid_rate;
+ } else
+ /* No acceptable divider - return original rate */
+ return tclk->rate;
+ }
+
+ if (tclk->flags & RATE_CKCTL) {
+ parent_rate = tclk->parent->rate;
+ ret =
+ prcm_clksel_round_rate(tclk->prcmid, parent_rate,
+ rate, &new_div);
+ if (ret == PRCM_PASS)
+ return parent_rate / new_div;
+ else
+ /* No acceptable divider - return original rate */
+ return tclk->rate;
+ }
+
+ if (tclk->round_rate != 0)
+ return tclk->round_rate(tclk, rate);
+
+ return tclk->rate;
+}
+
+/* Set the clock rate for a clock source */
+static int omap3_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+#ifdef ENABLE_CLOCKCONTROL
+ int ret = -EINVAL;
+ u32 validrate, parent_rate, mnoutput;
+ u32 new_div = 0;
+
+ pr_debug("Clock name: %s\n", clk->name);
+
+ /* For external mcbsp clock, the driver can set the rate using*/
+ /* clk_set_rate API */
+ if (clk == &ext_mcbsp_ck) {
+ clk->rate = rate;
+ clk->recalc(clk);
+ return 0;
+ }
+
+ if (!(clk->flags & VDD1_CONFIG_PARTICIPANT)
+ && !(clk->flags & VDD2_CONFIG_PARTICIPANT)) {
+ if (clk->flags & DPLL_OUTPUT) {
+ ret = prcm_get_dpll_mn_output(clk->prcmid, &mnoutput);
+ /*mnoutput has CLKOUT = (Freq*m)/n+1 in case dpll
+ *is locked or bypass clock if it is not locked */
+ if (ret != PRCM_PASS)
+ /* Signal error */
+ return (-EINVAL);
+ ret =
+ prcm_clksel_round_rate(clk->prcmid, (2 * mnoutput),
+ (rate / 1000), &new_div);
+ if (ret == PRCM_PASS) {
+ validrate = (2 * mnoutput * 1000) / new_div;
+ pr_debug("Valid rate: %d\n", validrate);
+ if (validrate != rate)
+ return (-EINVAL);
+ } else
+ /* No acceptable divider - signal error */
+ return (-EINVAL);
+ ret = prcm_configure_dpll_divider(clk->prcmid, new_div);
+ } else if (clk->flags & RATE_CKCTL) {
+ parent_rate = clk->parent->rate;
+ ret =
+ prcm_clksel_round_rate(clk->prcmid,
+ parent_rate, rate,
+ &new_div);
+ if (ret == PRCM_PASS) {
+ validrate = parent_rate / new_div;
+ pr_debug("Valid rate: %d\n", validrate);
+ if (validrate != rate)
+ return (ret);
+ } else
+ return (-EINVAL);
+ ret =
+ prcm_clksel_set_divider(clk->prcmid,
+ new_div);
+ if (ret != PRCM_PASS)
+ ret = -EINVAL;
+ } else if (clk->set_rate != 0) {
+ /*call clk specific rate func*/
+ ret = clk->set_rate(clk, rate);
+ }
+ }
+
+ if (ret == 0)
+ clk->recalc(clk);
+
+ return ret;
+#else
+ return 0;
+#endif
+}
+
+/* Change the parent of a clock */
+static int omap3_clk_set_parent(struct clk *cclk, struct clk *new_parent)
+{
+#ifdef ENABLE_CLOCKCONTROL
+ int ret = -EINVAL;
+
+ pr_debug("Clock name: %s, Parent name: %s\n", cclk->name,
+ new_parent->name);
+
+ if ((cclk->flags & VDD1_CONFIG_PARTICIPANT)
+ || (cclk->flags & VDD2_CONFIG_PARTICIPANT))
+ return ret;
+
+ if (!(cclk->flags & SRC_SEL))
+ return ret;
+
+ if (cclk->usecount > 0) /*if clock is currently active. */
+ _omap3_clk_disable(cclk); /* shut down clock to stop glitch */
+
+ ret = prcm_clk_set_source(cclk->prcmid, new_parent->prcmid);
+ if (ret != PRCM_PASS)
+ ret = -EINVAL;
+
+ if (cclk->usecount > 0)
+ _omap3_clk_enable(cclk);
+
+ if (ret == 0) {
+ cclk->parent = new_parent;
+ cclk->recalc(cclk);
+ }
+ return ret;
+#else
+ return 0;
+#endif
+}
+
+/* Return the parent of a clock */
+static struct clk *omap3_clk_get_parent(struct clk *clk)
+{
+ return clk->parent;
+}
+
+static void omap3_table_recalc(struct clk *clk)
+{
+ if ((clk != &virt_vdd1_prcm_set) && (clk != &virt_vdd2_prcm_set))
+ return;
+
+ if (clk == &virt_vdd1_prcm_set)
+ clk->rate = curr_vdd1_prcm_set->speed;
+ else
+ clk->rate = curr_vdd2_prcm_set->speed;
+ pr_debug("CLK RATE:%lu\n", clk->rate);
+}
+
+static long omap3_round_to_table_rate(struct clk *clk, unsigned long rate)
+{
+ struct vdd_prcm_config *ptr;
+ long highest_rate;
+
+ if ((clk != &virt_vdd1_prcm_set) && (clk != &virt_vdd2_prcm_set))
+ return -EINVAL;
+
+ highest_rate = -EINVAL;
+
+ if (clk == &virt_vdd1_prcm_set)
+ ptr = vdd1_rate_table + MAX_VDD1_OPP;
+ else
+ ptr = vdd2_rate_table + MAX_VDD2_OPP;
+
+ for (; ptr->speed; ptr--) {
+ highest_rate = ptr->speed;
+ pr_debug("Highest speed : %lu, rate: %lu\n"
+ , highest_rate, rate);
+ if (ptr->speed <= rate)
+ break;
+ }
+ return highest_rate;
+}
+
+static int omap3_select_table_rate(struct clk *clk, unsigned long rate)
+{
+#ifdef ENABLE_CLOCKCONTROL
+ u8 cpu_mask = 0;
+ u32 cur_vdd_rate, current_opp;
+ struct vdd_prcm_config *prcm_vdd;
+ unsigned long found_speed = 0;
+ int ret = -EINVAL;
+ int div = 0;
+
+ if ((clk != &virt_vdd1_prcm_set) && (clk != &virt_vdd2_prcm_set))
+ return ret;
+
+ if (cpu_is_omap3430())
+ cpu_mask = RATE_IN_343X;
+
+ if (clk == &virt_vdd1_prcm_set)
+ prcm_vdd = vdd1_rate_table + MAX_VDD1_OPP;
+ else
+ prcm_vdd = vdd2_rate_table + MAX_VDD2_OPP;
+
+ for (; prcm_vdd->speed; prcm_vdd--) {
+ if (!(prcm_vdd->flags & cpu_mask))
+ continue;
+ if (prcm_vdd->speed <= rate) {
+ found_speed = prcm_vdd->speed;
+ pr_debug("Found speed = %lu\n", found_speed);
+ break;
+ }
+ }
+
+ if (!found_speed) {
+ printk(KERN_INFO "Could not set table rate to %luMHz\n",
+ rate / 1000000);
+ return -EINVAL;
+ }
+
+ if (clk == &virt_vdd1_prcm_set) {
+ ret =
+ prcm_get_processor_speed(clk->parent->prcmid,
+ &cur_vdd_rate);
+ if (ret != PRCM_PASS)
+ return -EINVAL;
+ current_opp = curr_vdd1_prcm_set->opp;
+ } else {
+ ret = prcm_get_dpll_rate(clk->parent->prcmid,
+ &cur_vdd_rate);
+ if (ret != PRCM_PASS)
+ return -EINVAL;
+ /* Now cur_vdd_rate holds value of core_ck */
+ /* The divider for l3_ck */
+ ret = prcm_clksel_get_divider((&l3_ck)->prcmid, &div);
+ if ((ret != PRCM_PASS) || (div == 0))
+ return -EINVAL;
+ cur_vdd_rate /= div;
+ current_opp = curr_vdd2_prcm_set->opp;
+ }
+
+ cur_vdd_rate *= 1000;
+ pr_debug("Current rate:%u\n", cur_vdd_rate);
+ if (cur_vdd_rate != found_speed) {
+ ret =
+ prcm_do_frequency_scaling(prcm_vdd->opp,
+ current_opp);
+ if (ret != PRCM_PASS)
+ return -EINVAL;
+#ifdef CONFIG_CORE_OFF
+ save_scratchpad_contents();
+#endif
+ }
+
+ if (clk == &virt_vdd1_prcm_set) {
+ curr_vdd1_prcm_set = prcm_vdd;
+ omap3_clk_recalc(&mpu_ck);
+ omap3_propagate_rate(&mpu_ck);
+ omap3_clk_recalc(&iva2_ck);
+ omap3_propagate_rate(&iva2_ck);
+ /*Update loops_per_jiffy if processor speed is being changed*/
+ loops_per_jiffy = compute_lpj(loops_per_jiffy,
+ (cur_vdd_rate / 1000),
+ (found_speed / 1000));
+ } else {
+ curr_vdd2_prcm_set = prcm_vdd;
+ omap3_clk_recalc(&core_ck);
+ omap3_propagate_rate(&core_ck);
+ omap3_clk_recalc(&core_x2_ck);
+ omap3_propagate_rate(&core_x2_ck);
+ omap3_clk_recalc(&emul_core_alwon_ck);
+ omap3_propagate_rate(&emul_core_alwon_ck);
+ }
+
+#endif
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*
+ * Omap3 clock reset and init functions
+ *-------------------------------------------------------------------------*/
+
+/* If usecount of clock is 0, disable it */
+static void omap3_disable_unused_clocks(struct clk *clk)
+{
+ pr_debug("Disabling unused clock \"%s\"...\n ", clk->name);
+ _omap3_clk_disable(clk);
+}
+
+#ifdef CONFIG_CPU_FREQ
+static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(vdd1_rate_table)];
+
+void omap3_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+ struct vdd_prcm_config *prcm;
+ int i = 0;
+
+ prcm = vdd1_rate_table + MAX_VDD1_OPP - 1;
+ for (; prcm->speed; prcm--) {
+ freq_table[i].index = i;
+ freq_table[i].frequency = prcm->speed / 1000;
+ i++;
+ }
+
+ if (i == 0) {
+ printk(KERN_WARNING "%s: failed to initialize frequency \
+ table\n",
+ __FUNCTION__);
+ return;
+ }
+
+ freq_table[i].index = i;
+ freq_table[i].frequency = CPUFREQ_TABLE_END;
+
+ *table = &freq_table[0];
+}
+#endif
+
+/* Get the rate of oscillator by calling PRCM API */
+static void omap3_get_crystal_rate(struct clk *osc)
+{
+ osc->rate = prcm_get_crystal_rate() * 1000;
+ pr_debug("Rate:%lu\n", osc->rate);
+}
+
+static struct clk_functions omap3_clk_functions = {
+ .clk_enable = omap3_clk_enable,
+ .clk_disable = omap3_clk_disable,
+ .clk_round_rate = omap3_clk_round_rate,
+ .clk_set_rate = omap3_clk_set_rate,
+ .clk_set_parent = omap3_clk_set_parent,
+ .clk_get_parent = omap3_clk_get_parent,
+ .clk_disable_unused = omap3_disable_unused_clocks,
+#ifdef CONFIG_CPU_FREQ
+ .clk_init_cpufreq_table = omap3_clk_init_cpufreq_table,
+#endif
+};
+
+/*
+ * Set clocks for bypass mode for reboot to work.
+ */
+void omap3_clk_prepare_for_reboot(void)
+{
+ /* Will be implemented when frequency change code is in place */
+ return;
+}
+
+/* Get the parent clocks by reading registers and populate
+ the clock nodes with the correct parent information */
+static int omap3_update_sources(void)
+{
+ struct clk **clkptr;
+ struct clk *cp;
+ u32 pid = 0, ret = -EINVAL;
+
+ for (clkptr = onchip_clks;
+ clkptr < onchip_clks + ARRAY_SIZE(onchip_clks); clkptr++) {
+ cp = *clkptr;
+ if (cp->flags & SRC_SEL) {
+ ret = prcm_clk_get_source(cp->prcmid, &pid);
+ if (ret != PRCM_PASS) {
+ pr_debug(KERN_ERR
+ "prcm_clk_get_source returned error for %s\n",
+ cp->name);
+ return -EINVAL;
+ }
+ switch (cp->prcmid) {
+ case PRCM_48M_FCLK:
+ if (pid == PRCM_DPLL4_M2X2_CLK)
+ cp->parent = &func_96m_ck;
+ else
+ cp->parent = &sys_alt_ck;
+ break;
+ case PRCM_USIM:
+ if (pid == PRCM_SYS_CLK)
+ cp->parent = &sys_ck;
+ else if (pid == PRCM_DPLL4_M2X2_CLK)
+ cp->parent = &cm_96m_ck;
+ else
+ cp->parent = &ext_mcbsp_ck;
+ break;
+ case PRCM_96M_CLK:
+ if (pid == PRCM_DPLL4_M2X2_CLK)
+ cp->parent = &cm_96m_ck;
+ else
+ cp->parent = &sys_ck;
+ break;
+ case PRCM_SYS_CLKOUT2:
+ if (pid == PRCM_DPLL3_M2_CLK)
+ cp->parent = &core_ck;
+ else if (pid == PRCM_SYS_CLK)
+ cp->parent = &sys_ck;
+ else if (pid == PRCM_DPLL4_M2X2_CLK)
+ cp->parent = &func_96m_ck;
+ break;
+ case PRCM_MCBSP1:
+ case PRCM_MCBSP2:
+ case PRCM_MCBSP3:
+ case PRCM_MCBSP4:
+ case PRCM_MCBSP5:
+ if (pid == PRCM_DPLL4_M2X2_CLK)
+ cp->parent = &func_96m_ck;
+ else
+ cp->parent = &ext_mcbsp_ck;
+ break;
+ case PRCM_GPT1:
+ case PRCM_GPT2:
+ case PRCM_GPT3:
+ case PRCM_GPT4:
+ case PRCM_GPT5:
+ case PRCM_GPT6:
+ case PRCM_GPT7:
+ case PRCM_GPT8:
+ case PRCM_GPT9:
+ case PRCM_GPT10:
+ case PRCM_GPT11:
+ if (pid == PRCM_SYS_32K_CLK)
+ cp->parent = &sys_32k_ck;
+ else
+ cp->parent = &sys_ck;
+
+ }
+ pr_debug("Parent updated for clock: %s\n", cp->name);
+ pr_debug("Parent name: %s\n", cp->parent->name);
+ }
+ }
+ return 0;
+}
+
+/* Arch specific init */
+static int __init omap3_clk_arch_init(void)
+{
+ struct vdd_prcm_config *vdd1_prcm;
+ struct vdd_prcm_config *vdd2_prcm;
+ u32 sys_clk_speed, mpu_speed, core_speed, l3_speed = 0;
+ int div;
+
+ /* Lock DPLL5 */
+ if (prcm_configure_dpll(DPLL5_PER2, -1, -1, -1))
+ panic("FATAL ERROR: Unable to Configure DPLL5\n");
+ if (prcm_enable_dpll(DPLL5_PER2))
+ panic("FATAL ERROR: Unable to Lock DPLL5\n");
+ omap3_get_crystal_rate(&osc_ck);
+ omap3_update_sources();
+
+ sys_clk_speed = prcm_get_system_clock_speed() * 1000;
+ prcm_get_processor_speed(DOM_MPU, &mpu_speed);
+ mpu_speed = mpu_speed * 1000;
+ prcm_get_dpll_rate((&core_ck)->prcmid, &core_speed);
+ core_speed = core_speed * 1000;
+ prcm_clksel_get_divider((&l3_ck)->prcmid, &div);
+ if (div != 0)
+ l3_speed = core_speed / div;
+ else
+ printk(KERN_ERR"Error: Divider for L3 returned 0 in omap3_clk"
+ "_arch_init\n");
+
+ pr_debug("System clock speed: %u, mpu speed : %u, l3_speed : %u"
+ "\n", sys_clk_speed, mpu_speed, l3_speed);
+
+ for (vdd1_prcm = vdd1_rate_table+MAX_VDD1_OPP; vdd1_prcm->speed;
+ vdd1_prcm--) {
+ pr_debug("%lu\n", vdd1_prcm->speed);
+ if (vdd1_prcm->speed <= mpu_speed)
+ break;
+ }
+ curr_vdd1_prcm_set = vdd1_prcm;
+
+ for (vdd2_prcm = vdd2_rate_table+MAX_VDD2_OPP; vdd2_prcm->speed;
+ vdd2_prcm++) {
+ pr_debug("%lu\n", vdd2_prcm->speed);
+ if (vdd2_prcm->speed <= l3_speed)
+ break;
+ }
+ curr_vdd2_prcm_set = vdd2_prcm;
+
+ propagate_rate(&osc_ck); /* update main root fast */
+ propagate_rate(&sys_32k_ck); /* update main root slow */
+ propagate_rate(&sys_alt_ck); /* update alt ck tree */
+
+ pr_debug("Rate propagation done for all clocks\n");
+ return 0;
+}
+
+arch_initcall(omap3_clk_arch_init);
+
+int __init omap3_clk_init(void)
+{
+ struct clk **clkp;
+
+ clk_init(&omap3_clk_functions);
+
+ for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
+ clkp++) {
+
+ if ((*clkp)->flags & CLOCK_IN_OMAP343X) {
+ clk_register(*clkp);
+#ifdef CONFIG_TRACK_RESOURCES
+ (*clkp)->clk_got.prev = &(*clkp)->clk_got;
+ (*clkp)->clk_got.next = &(*clkp)->clk_got;
+ (*clkp)->clk_enabled.prev = &(*clkp)->clk_enabled;
+ (*clkp)->clk_enabled.next = &(*clkp)->clk_enabled;
+#endif
+ continue;
+ }
+ }
+
+#ifdef CONFIG_OMAP34XX_OFFMODE
+ spin_lock_init(&inatimer_lock);
+ init_timer(&coredomain_timer);
+ init_timer(&perdomain_timer);
+
+ coredomain_timer.function = coredomain_timer_func;
+ perdomain_timer.function = perdomain_timer_func;
+#endif /* #ifdef CONFIG_OMAP34XX_OFFMODE */
+
+ return 0;
+}
+
+int __init omap2_clk_init(void)
+{
+ return omap3_clk_init();
+}
Index: git-latest5/arch/arm/mach-omap2/clock_34xx.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ git-latest5/arch/arm/mach-omap2/clock_34xx.h 2008-02-29 20:29:47.056287920 +0530
@@ -0,0 +1,1529 @@
+/*
+ * linux/arch/arm/mach-omap2/clock_34xx.h
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Karthik Dasu <karthik-dp@xxxxxx>
+ *
+ * Based on OMAP2 clock framework created by
+ * Richard Woodruff <r-woodruff2@xxxxxx>
+ *
+ * Copyright (C) 2004 Nokia corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen@xxxxxxxxxxxxxx>
+ * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP3_CLOCK_H
+#define __ARCH_ARM_MACH_OMAP3_CLOCK_H
+
+#include <asm/arch/prcm_34xx.h>
+
+/* Macro to enable clock control via clock framework */
+#define ENABLE_CLOCKCONTROL 1
+
+static void omap3_clk_recalc(struct clk *clk);
+static void omap3_followparent_recalc(struct clk *clk);
+static void omap3_propagate_rate(struct clk *clk);
+static void omap3_table_recalc(struct clk *clk);
+static long omap3_round_to_table_rate(struct clk *clk, unsigned long rate);
+static int omap3_select_table_rate(struct clk *clk, unsigned long rate);
+
+#ifdef CONFIG_OMAP34XX_OFFMODE
+extern void context_save_done(struct clk *clk);
+extern void save_scratchpad_contents(void);
+#endif /* #ifdef CONFIG_OMAP34XX_OFFMODE */
+
+/*-------------------------------------------------------------------------
+ * 34xx clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In many
+ * cases the parent is selectable. The get/set parent calls will also
+ * switch sources.
+ *
+ * Several sources are given initial rates which may be wrong, this will
+ * be fixed up in the init func.
+ *
+ * Things are broadly separated below by clock domains. It is
+ * noteworthy that most periferals have dependencies on multiple clock
+ * domains. Many get their interface clocks from the L4 domain, but get
+ * functional clocks from fixed sources or other core domain derived
+ * clocks.
+ *-------------------------------------------------------------------------*/
+
+/* initial hardcode defines */
+#define S_OSC 19200000
+#define S_32K 32768
+#define S_ALT 54000000
+
+#define S12M 12000000
+#define S13M 13000000
+#define S19M 19200000
+#define S26M 26000000
+#define S38M 38400000
+
+#define S625M 625000000
+#define S550M 550000000
+#define S500M 500000000
+#define S250M 250000000
+#define S125M 125000000
+#define S19M 19200000
+#define S120M 120000000
+
+#define S96M 96000000
+#define S166M 166000000
+#define S83M 83000000
+
+#define SRC_SEL (1 << 9) /* Source of the clock
+ *can be changed */
+#define VDD1_CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
+#define VDD2_CONFIG_PARTICIPANT (1 << 11) /* Fundamental clock */
+#define F_CLK (1 << 12) /* Functional clock */
+#define I_CLK (1 << 13) /* Interface clock */
+#define DPLL_OUTPUT (1 << 14) /* DPLL output */
+#define POWER_ON_REQUIRED (1 << 28) /* For devices which
+ *need to be powered on */
+
+struct vdd_prcm_config {
+ unsigned long speed;
+ unsigned long opp;
+ unsigned char flags;
+};
+
+static struct vdd_prcm_config vdd1_rate_table[] = {
+ {0, 0, 0},
+ /*OPP1*/
+ {S125M, PRCM_VDD1_OPP1, RATE_IN_343X},
+ /*OPP2*/
+ {S250M, PRCM_VDD1_OPP2, RATE_IN_343X},
+ /*OPP3*/
+ {S500M, PRCM_VDD1_OPP3, RATE_IN_343X},
+ /*OPP4*/
+ {S550M, PRCM_VDD1_OPP4, RATE_IN_343X},
+ /*OPP5*/
+ {S625M, PRCM_VDD1_OPP5, RATE_IN_343X},
+};
+
+static struct vdd_prcm_config vdd2_rate_table[] = {
+ {0, 0, 0},
+ /*OPP1*/
+ {S19M, PRCM_VDD2_OPP1, RATE_IN_343X},
+ /*OPP2*/
+ {S83M, PRCM_VDD2_OPP2, RATE_IN_343X},
+ /*OPP3*/
+ {S166M, PRCM_VDD2_OPP3, RATE_IN_343X},
+};
+#define MAX_VDD1_OPP 5
+#define MAX_VDD2_OPP 3
+
+/* Base external input clocks */
+/* 32K clock */
+static struct clk sys_32k_ck = {
+ .name = "sys_32k_ck",
+ .prcmid = PRCM_SYS_32K_CLK,
+ .rate = S_32K,
+ .flags = CLOCK_IN_OMAP343X | RATE_FIXED |
+ ALWAYS_ENABLED | RATE_PROPAGATES,
+ .recalc = &omap3_propagate_rate,
+};
+
+static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
+ .name = "osc_ck",
+ .rate = S_OSC, /* fixed up in clock init */
+ .flags = CLOCK_IN_OMAP343X | RATE_FIXED |
+ ALWAYS_ENABLED | RATE_PROPAGATES,
+ .recalc = &omap3_propagate_rate,
+};
+
+static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
+ .name = "sys_ck", /* ~ ref_clk also */
+ .parent = &osc_ck,
+ .rate = S_OSC,
+ .prcmid = PRCM_SYS_CLK,
+ .flags = CLOCK_IN_OMAP343X | RATE_FIXED |
+ ALWAYS_ENABLED | RATE_PROPAGATES,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk sys_alt_ck = {
+ .name = "sys_alt_ck",
+ .rate = S_ALT,
+ .prcmid = PRCM_SYS_ALT_CLK,
+ .flags = CLOCK_IN_OMAP343X | RATE_FIXED |
+ ALWAYS_ENABLED | RATE_PROPAGATES,
+ .recalc = &omap3_propagate_rate,
+};
+
+static struct clk usim_fck = {
+ .name = "usim_fck",
+ .parent = &sys_ck,
+ .prcmid = PRCM_USIM,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | RATE_CKCTL | SRC_SEL,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk usim_ick = {
+ .name = "usim_ick",
+ .parent = &sys_ck,
+ .prcmid = PRCM_USIM,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk usbhost2_fck = {
+ .name = "usbhost2_fck",
+ .parent = &sys_ck,
+ .prcmid = PRCM_USBHOST2,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | DPLL_OUTPUT | POWER_ON_REQUIRED,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk core_ck = { /* Same as DPLL3_M2_CLK */
+ .name = "core_ck",
+ .parent = &sys_ck,
+ .prcmid = PRCM_DPLL3_M2_CLK,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED |
+ RATE_PROPAGATES | DPLL_OUTPUT | VDD2_CONFIG_PARTICIPANT,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk core_x2_ck = { /* Same as DPLL3_M2X2_CLK */
+ .name = "core_x2_ck",
+ .parent = &sys_ck,
+ .prcmid = PRCM_DPLL3_M2X2_CLK,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED |
+ RATE_PROPAGATES | DPLL_OUTPUT | VDD2_CONFIG_PARTICIPANT,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk cpefuse_fck = {
+ .name = "cpefuse_fck",
+ .parent = &sys_ck,
+ .prcmid = PRCM_CPEFUSE,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk ts_fck = {
+ .name = "ts_fck",
+ .parent = &sys_32k_ck,
+ .prcmid = PRCM_TS,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk emul_core_alwon_ck = { /* Same as DPLL3_M3X2_CLK */
+ .name = "emul_core_alwon_ck",
+ .parent = &sys_ck,
+ .prcmid = PRCM_DPLL3_M3X2_CLK,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED |
+ RATE_PROPAGATES | DPLL_OUTPUT,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk cm_96m_ck = { /* same as DPLL4_M2X2_CLK */
+ .name = "cm_96m_ck",
+ .parent = &sys_ck,
+ .prcmid = PRCM_DPLL4_M2X2_CLK,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED |
+ RATE_PROPAGATES | DPLL_OUTPUT,
+ .recalc = &omap3_clk_recalc,
+
+};
+
+static struct clk func_96m_ck = {
+ .name = "func_96m_ck",
+ .parent = &sys_ck,
+ .prcmid = PRCM_96M_CLK,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED |
+ RATE_PROPAGATES | SRC_SEL,
+ .recalc = &omap3_followparent_recalc,
+
+};
+
+static struct clk dpll4_m3x2_ck = {
+ .name = "dpll4_m3x2_ck",
+ .parent = &sys_ck,
+ .prcmid = PRCM_DPLL4_M3X2_CLK,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED |
+ RATE_PROPAGATES | DPLL_OUTPUT,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk emul_per_alwon_ck = { /* same as DPLL4_M6X2_CLK */
+ .name = "emul_per_alwon_ck",
+ .parent = &sys_ck,
+ .prcmid = PRCM_DPLL4_M6X2_CLK,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED |
+ RATE_PROPAGATES | DPLL_OUTPUT,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk func_48m_ck = {
+ .name = "func_48m_ck",
+ .parent = &func_96m_ck, /*can be sys_alt_ck too */
+ .prcmid = PRCM_48M_FCLK,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ ALWAYS_ENABLED | RATE_CKCTL | SRC_SEL,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk func_12m_ck = {
+ .name = "func_12m_ck",
+ .parent = &func_48m_ck,
+ .prcmid = PRCM_12M_FCLK,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ ALWAYS_ENABLED | RATE_CKCTL,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk dss_tv_fck = {
+ /* This node controls dss_96m_fck too */
+ .name = "dss_tv_fck",
+ .parent = &dpll4_m3x2_ck, /*can be sys_alt_ck too */
+ .prcmid = PRCM_TVOUT,
+ .flags = CLOCK_IN_OMAP343X | SRC_SEL | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+/* External output clocks */
+static struct clk sys_clkout1 = {
+/*May need to revisit this - sys_clkout1 can be output clock too */
+ .name = "sys_clkout1",
+ .parent = &osc_ck,
+ .prcmid = PRCM_SYS_CLKOUT1,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk sys_clkout2 = {
+ .name = "sys_clkout2",
+ .parent = &sys_ck,
+/* Can be core_ck,dss_tv_fck or func_96m_ck too */
+ .prcmid = PRCM_SYS_CLKOUT2,
+ .flags = CLOCK_IN_OMAP343X | RATE_CKCTL | SRC_SEL,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk l3_ck = {
+ .name = "l3_ck",
+ .parent = &core_ck,
+ .prcmid = PRCM_L3_ICLK,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED |
+ RATE_PROPAGATES | RATE_CKCTL | VDD2_CONFIG_PARTICIPANT,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk gpmc_fck = {
+ .name = "gpmc_fck",
+ .parent = &l3_ck,
+ .prcmid = PRCM_GPMC,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | VDD2_CONFIG_PARTICIPANT,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk l4_ck = {
+ .name = "l4_ck",
+ .parent = &l3_ck,
+ .prcmid = PRCM_L4_ICLK,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED |
+ RATE_PROPAGATES | RATE_CKCTL | VDD2_CONFIG_PARTICIPANT,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk rm_ck = {
+ .name = "rm_ck",
+ .parent = &l4_ck,
+ .prcmid = PRCM_RM_ICLK,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED |
+ RATE_PROPAGATES | RATE_CKCTL | VDD2_CONFIG_PARTICIPANT,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk dpll1_fck = {
+ .name = "dpll1_fck",
+ .parent = &core_ck,
+ .prcmid = PRCM_DPLL1_FCLK,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED |
+ RATE_PROPAGATES | RATE_CKCTL,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk dpll2_fck = {
+ .name = "dpll2_fck",
+ .parent = &core_ck,
+ .prcmid = PRCM_DPLL2_FCLK,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED |
+ RATE_PROPAGATES | RATE_CKCTL,
+ .recalc = &omap3_clk_recalc,
+};
+
+/* Clocks in MPU Power Domain */
+static struct clk mpu_ck = { /* Control cpu */
+ .name = "mpu_ck",
+ .parent = &sys_ck,
+ .prcmid = DOM_MPU,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED |
+ RATE_PROPAGATES | VDD1_CONFIG_PARTICIPANT,
+ .recalc = &omap3_clk_recalc,
+};
+
+/* Clocks in IVA2 Power Domain */
+static struct clk iva2_ck = {
+ .name = "iva2_ck",
+ .parent = &sys_ck,
+ .prcmid = PRCM_IVA2,
+ .flags = CLOCK_IN_OMAP343X | F_CLK |
+ RATE_PROPAGATES | VDD1_CONFIG_PARTICIPANT | POWER_ON_REQUIRED,
+ .recalc = &omap3_clk_recalc,
+};
+
+/* GFX domain clocks */
+/* In the GFX domain, GFX_L3_FCLK and GFX_L3_ICLK are derived
+ from l3_iclk and have one gating control bit (CM_ICLKEN_GFX.EN_GFX).
+ So another clock (gfx_l3_ck) is represented in the clock tree with
+ two child clocks - gfx_fclk and gfx_iclk
+ When either of these child clocks are enabled, the EN_GFX bit will
+ be set to 1, making sure that the clock is supplied */
+
+static struct clk sgx_fck = {
+ .name = "sgx_fck",
+ .parent = &core_ck,
+ .flags = CLOCK_IN_OMAP343X | SRC_SEL | F_CLK | RATE_CKCTL |
+ POWER_ON_REQUIRED,
+ .prcmid = PRCM_SGX_FCLK,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk sgx_ick = {
+ .name = "sgx_ick",
+ .parent = &l3_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .prcmid = PRCM_SGX_ICLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk hsusb_ick = {
+ .name = "hsusb_ick",
+ .parent = &l3_ck,
+ .prcmid = PRCM_HSOTG,
+ .flags = CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk usbhost_ick = {
+ .name = "usbhost_ick",
+ .parent = &l3_ck,
+ .prcmid = PRCM_USBHOST1,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk usbhost1_fck = {
+ .name = "usbhost1_fck",
+ .parent = &func_48m_ck,
+ .prcmid = PRCM_USBHOST1,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk sdrc_ick = {
+ .name = "sdrc_ick",
+ .parent = &l3_ck,
+ .prcmid = PRCM_SDRC,
+ .flags = CLOCK_IN_OMAP343X | I_CLK | ALWAYS_ENABLED | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk pka_ick = {
+ .name = "pka_ick",
+ .parent = &l3_ck,
+ .prcmid = PRCM_PKA,
+ .flags = CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk aes2_ick = {
+ .name = "aes2_ick",
+ .parent = &l3_ck,
+ .prcmid = PRCM_AES2,
+ .flags = CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk sha12_ick = {
+ .name = "sha12_ick",
+ .parent = &l3_ck,
+ .prcmid = PRCM_SHA12,
+ .flags = CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk des2_ick = {
+ .name = "des2_ick",
+ .parent = &l3_ck,
+ .prcmid = PRCM_DES2,
+ .flags = CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk aes1_ick = {
+ .name = "aes1_ick",
+ .parent = &l4_ck,
+ .prcmid = PRCM_AES1,
+ .flags = CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk sha11_ick = {
+ .name = "sha11_ick",
+ .parent = &l4_ck,
+ .prcmid = PRCM_SHA11,
+ .flags = CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk des1_ick = {
+ .name = "des1_ick",
+ .parent = &l4_ck,
+ .prcmid = PRCM_DES1,
+ .flags = CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk rng1_ick = {
+ .name = "rng1_ick",
+ .parent = &l4_ck,
+ .prcmid = PRCM_RNG,
+ .flags = CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcbsp1_fck = {
+ .name = "mcbsp1_fck",
+ .parent = &func_96m_ck, /* Can also be external clock */
+ .prcmid = PRCM_MCBSP1,
+ .flags = CLOCK_IN_OMAP343X | SRC_SEL | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcbsp1_ick = {
+ .name = "mcbsp1_ick",
+ .parent = &l4_ck,
+ .prcmid = PRCM_MCBSP1,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcbsp5_fck = {
+ .name = "mcbsp5_fck",
+ .parent = &func_96m_ck, /* Can be external clock too */
+ .prcmid = PRCM_MCBSP5,
+ .flags = CLOCK_IN_OMAP343X | SRC_SEL | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcbsp5_ick = {
+ .name = "mcbsp5_ick",
+ .parent = &l4_ck,
+ .prcmid = PRCM_MCBSP5,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mmc1_fck = {
+ .name = "mmc_fck",
+ .id = 1,
+ .prcmid = PRCM_MMC1,
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mmc1_ick = {
+ .name = "mmc_ick",
+ .id = 1,
+ .prcmid = PRCM_MMC1,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mmc2_fck = {
+ .name = "mmc_fck",
+ .id = 2,
+ .prcmid = PRCM_MMC2,
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mmc2_ick = {
+ .name = "mmc_ick",
+ .id = 2,
+ .prcmid = PRCM_MMC2,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mmc3_fck = {
+ .name = "mmc_fck",
+ .id = 3,
+ .prcmid = PRCM_MMC3,
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mmc3_ick = {
+ .name = "mmc_ick",
+ .id = 3,
+ .prcmid = PRCM_MMC3,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mspro_ick = {
+ .name = "mspro_ick",
+ .prcmid = PRCM_MSPRO,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mspro_fck = {
+ .name = "mspro_fck",
+ .prcmid = PRCM_MSPRO,
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk i2c1_fck = {
+ .name = "i2c_fck",
+ .id = 1,
+ .prcmid = PRCM_I2C1,
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk i2c1_ick = {
+ .name = "i2c_ick",
+ .id = 1,
+ .prcmid = PRCM_I2C1,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk i2c2_fck = {
+ .name = "i2c_fck",
+ .id = 2,
+ .prcmid = PRCM_I2C2,
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk i2c2_ick = {
+ .name = "i2c_ick",
+ .id = 2,
+ .prcmid = PRCM_I2C2,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk i2c3_fck = {
+ .name = "i2c_fck",
+ .id = 3,
+ .prcmid = PRCM_I2C3,
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk i2c3_ick = {
+ .name = "i2c_ick",
+ .id = 3,
+ .prcmid = PRCM_I2C3,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk usbtll_host_sar_fck = {
+ .name = "usbtll_host_sar_fck",
+ .prcmid = PRCM_USBTLL,
+ .parent = &sys_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk usbtll_ick = {
+ .name = "usbtll_ick",
+ .prcmid = PRCM_USBTLL,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk uart1_fck = {
+ .name = "uart1_fck",
+ .prcmid = PRCM_UART1,
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk uart1_ick = {
+ .name = "uart1_ick",
+ .prcmid = PRCM_UART1,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk uart2_fck = {
+ .name = "uart2_fck",
+ .prcmid = PRCM_UART2,
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk uart2_ick = {
+ .name = "uart2_ick",
+ .prcmid = PRCM_UART2,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcspi1_fck = {
+ .name = "mcspi_fck",
+ .id = 1,
+ .prcmid = PRCM_MCSPI1,
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcspi1_ick = {
+ .name = "mcspi_ick",
+ .id = 1,
+ .prcmid = PRCM_MCSPI1,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcspi2_fck = {
+ .name = "mcspi_fck",
+ .id = 2,
+ .prcmid = PRCM_MCSPI2,
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcspi2_ick = {
+ .name = "mcspi_ick",
+ .id = 2,
+ .prcmid = PRCM_MCSPI2,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcspi3_fck = {
+ .name = "mcspi_fck",
+ .id = 3,
+ .prcmid = PRCM_MCSPI3,
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcspi3_ick = {
+ .name = "mcspi_ick",
+ .id = 3,
+ .prcmid = PRCM_MCSPI3,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcspi4_fck = {
+ .name = "mcspi_fck",
+ .id = 4,
+ .prcmid = PRCM_MCSPI4,
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcspi4_ick = {
+ .name = "mcspi_ick",
+ .id = 4,
+ .prcmid = PRCM_MCSPI4,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk hdq_fck = {
+ .name = "hdq_fck",
+ .prcmid = PRCM_HDQ,
+ .parent = &func_12m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk hdq_ick = {
+ .name = "hdq_ick",
+ .prcmid = PRCM_HDQ,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt10_fck = {
+ .name = "gpt10_fck",
+ .prcmid = PRCM_GPT10,
+ /* Can be sys_32k_fck too */
+ .parent = &sys_ck,
+ .rate = S_OSC,
+ .flags = CLOCK_IN_OMAP343X | SRC_SEL | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt10_ick = {
+ .name = "gpt10_ick",
+ .prcmid = PRCM_GPT10,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt11_fck = {
+ .name = "gpt11_fck",
+ .prcmid = PRCM_GPT11,
+ /* Can be sys_32k_fck too */
+ .parent = &sys_ck,
+ .rate = S_OSC,
+ .flags = CLOCK_IN_OMAP343X | SRC_SEL | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt11_ick = {
+ .name = "gpt11_ick",
+ .prcmid = PRCM_GPT11,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk omapctrl_ick = {
+ .name = "omapctrl_ick",
+ .prcmid = PRCM_OMAP_CTRL,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mailboxes_ick = {
+ .name = "mailboxes_ick",
+ .prcmid = PRCM_MBOXES,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk ssi_ick = {
+ .name = "ssi_ick",
+ .prcmid = PRCM_SSI,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk ssi_ssr_sst_fck = {
+/* This clock node is used to represent both ssi_ssr_fclk
+ * and ssi_sst_fclk since there is one enable bit for both */
+ .name = "ssi_ssr_sst_fck",
+ .prcmid = PRCM_SSI,
+ .parent = &core_x2_ck,
+ /*Rate of ssi_sst = ssi_ssr rate/2 */
+ .flags = CLOCK_IN_OMAP343X | RATE_CKCTL | F_CLK,
+ .recalc = &omap3_clk_recalc,
+};
+
+/* DSS domain clocks */
+static struct clk dss1_fck = {
+ .name = "dss1_alwon_fck",
+ .prcmid = PRCM_DSS,
+ .parent = &sys_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | DPLL_OUTPUT | POWER_ON_REQUIRED,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk dss_96m_fck = {
+ .name = "dss_96m_fck",
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk dss2_fck = {
+ .name = "dss2_fck",
+ .prcmid = PRCM_DSS2,
+ .parent = &sys_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk dss_ick = {
+ /* This node models both DSS_L3 and DSS_L4 clocks */
+ .name = "dss_ick",
+ .prcmid = PRCM_DSS,
+ .parent = &l3_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk cam_ick = {
+ /* Models both CAM_L3 and CAM_L4 clocks */
+ .name = "cam_ick",
+ .prcmid = PRCM_CAM,
+ .parent = &l3_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk cam_fck = {
+ .name = "cam_fck",
+ .prcmid = PRCM_CAM,
+ .parent = &sys_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | DPLL_OUTPUT | POWER_ON_REQUIRED,
+ .recalc = &omap3_clk_recalc,
+};
+
+static struct clk csi2_fck = {
+ .name = "csi2_fck",
+ .prcmid = PRCM_CSI2,
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt1_ick = {
+ .name = "gpt1_ick",
+ .prcmid = PRCM_GPT1,
+ .parent = &sys_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt1_fck = {
+ .name = "gpt1_fck",
+ .prcmid = PRCM_GPT1,
+ /* Can be sys_ck too */
+ .parent = &sys_32k_ck,
+ .rate = S_32K,
+ .flags = CLOCK_IN_OMAP343X | SRC_SEL | F_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk sync_32k_ick = {
+ .name = "omap_32ksync_ick",
+ .prcmid = PRCM_32KSYNC,
+ .parent = &sys_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk sync_32k_fck = {
+ .name = "sync_32k_fck",
+ .parent = &sys_32k_ck,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk wdt2_ick = {
+ .name = "wdt_ick",
+ .id = 2,
+ .prcmid = PRCM_WDT2,
+ .parent = &sys_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk wdt2_fck = {
+ .name = "wdt_fck",
+ .id = 2,
+ .prcmid = PRCM_WDT2,
+ .parent = &sys_32k_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpio1_fck = {
+ .name = "gpio1_fck",
+ .prcmid = PRCM_GPIO1,
+ .parent = &sys_32k_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpio1_ick = {
+ .name = "gpio1_ick",
+ .prcmid = PRCM_GPIO1,
+ .parent = &sys_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt12_ick = {
+ .name = "gpt12_ick",
+ .prcmid = PRCM_GPT12,
+ .parent = &sys_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt12_fck = {
+ .name = "gpt12_fck",
+ .parent = &sys_32k_ck,
+ .rate = S_32K,
+ /* No s/w control for this clock */
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk wdt1_ick = {
+ .name = "wdt_ick",
+ .id = 1,
+ .prcmid = PRCM_WDT1,
+ .parent = &sys_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk wdt1_fck = {
+ .name = "wdt_fck",
+ .id = 1,
+ .parent = &sys_32k_ck,
+ /* No s/w control for this clock */
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcbsp2_fck = {
+ .name = "mcbsp2_fck",
+ .parent = &func_96m_ck, /*Can be external clock too */
+ .prcmid = PRCM_MCBSP2,
+ .flags = CLOCK_IN_OMAP343X | SRC_SEL | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcbsp2_ick = {
+ .name = "mcbsp2_ick",
+ .parent = &l4_ck,
+ .prcmid = PRCM_MCBSP2,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcbsp3_fck = {
+ .name = "mcbsp3_fck",
+ .parent = &func_96m_ck, /* Can be external clock too */
+ .prcmid = PRCM_MCBSP3,
+ .flags = CLOCK_IN_OMAP343X | SRC_SEL | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcbsp3_ick = {
+ .name = "mcbsp3_ick",
+ .parent = &l4_ck,
+ .prcmid = PRCM_MCBSP3,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcbsp4_fck = {
+ .name = "mcbsp4_fck",
+ .parent = &func_96m_ck, /* can be external clock too */
+ .prcmid = PRCM_MCBSP4,
+ .flags = CLOCK_IN_OMAP343X | SRC_SEL | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk mcbsp4_ick = {
+ .name = "mcbsp4_ick",
+ .parent = &l4_ck,
+ .prcmid = PRCM_MCBSP4,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk uart3_ick = {
+ .name = "uart3_ick",
+ .prcmid = PRCM_UART3,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk uart3_fck = {
+ .name = "uart3_fck",
+ .prcmid = PRCM_UART3,
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk wdt3_fck = {
+ .name = "wdt_fck",
+ .id = 3,
+ .prcmid = PRCM_WDT3,
+ .parent = &sys_32k_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk wdt3_ick = {
+ .name = "wdt_ick",
+ .id = 3,
+ .prcmid = PRCM_WDT3,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpio2_fck = {
+ .name = "gpio2_fck",
+ .prcmid = PRCM_GPIO2,
+ .parent = &sys_32k_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpio2_ick = {
+ .name = "gpio2_ick",
+ .prcmid = PRCM_GPIO2,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpio3_fck = {
+ .name = "gpio3_fck",
+ .prcmid = PRCM_GPIO3,
+ .parent = &sys_32k_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpio3_ick = {
+ .name = "gpio3_ick",
+ .prcmid = PRCM_GPIO3,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpio4_fck = {
+ .name = "gpio4_fck",
+ .prcmid = PRCM_GPIO4,
+ .parent = &sys_32k_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpio4_ick = {
+ .name = "gpio4_ick",
+ .prcmid = PRCM_GPIO4,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpio5_fck = {
+ .name = "gpio5_fck",
+ .prcmid = PRCM_GPIO5,
+ .parent = &sys_32k_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpio5_ick = {
+ .name = "gpio5_ick",
+ .prcmid = PRCM_GPIO5,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpio6_fck = {
+ .name = "gpio6_fck",
+ .prcmid = PRCM_GPIO6,
+ .parent = &sys_32k_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpio6_ick = {
+ .name = "gpio6_ick",
+ .prcmid = PRCM_GPIO6,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt2_ick = {
+ .name = "gpt2_ick",
+ .prcmid = PRCM_GPT2,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt2_fck = {
+ .name = "gpt2_fck",
+ .prcmid = PRCM_GPT2,
+ .parent = &sys_ck, /* can be sys_32k_ck too */
+ .rate = S_OSC,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | SRC_SEL | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt3_ick = {
+ .name = "gpt3_ick",
+ .prcmid = PRCM_GPT3,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt3_fck = {
+ .name = "gpt3_fck",
+ .prcmid = PRCM_GPT3,
+ .parent = &sys_ck, /* Can be sys_32k_ck too */
+ .rate = S_OSC,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | SRC_SEL | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt4_ick = {
+ .name = "gpt4_ick",
+ .prcmid = PRCM_GPT4,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt4_fck = {
+ .name = "gpt4_fck",
+ .prcmid = PRCM_GPT4,
+ .parent = &sys_ck, /* Can be sys_32k_ck too */
+ .rate = S_OSC,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | SRC_SEL | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt5_ick = {
+ .name = "gpt5_ick",
+ .prcmid = PRCM_GPT5,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt5_fck = {
+ .name = "gpt5_fck",
+ .prcmid = PRCM_GPT5,
+ .parent = &sys_ck, /* Can be sys_32k_ck too */
+ .rate = S_OSC,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | SRC_SEL | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt6_ick = {
+ .name = "gpt6_ick",
+ .prcmid = PRCM_GPT6,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt6_fck = {
+ .name = "gpt6_fck",
+ .prcmid = PRCM_GPT6,
+ .parent = &sys_ck, /* Can be sys_32k_ck too */
+ .rate = S_OSC,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | SRC_SEL | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt7_ick = {
+ .name = "gpt7_ick",
+ .prcmid = PRCM_GPT7,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt7_fck = {
+ .name = "gpt7_fck",
+ .prcmid = PRCM_GPT7,
+ .parent = &sys_ck, /* Can be sys_32k_ck too */
+ .rate = S_OSC,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | SRC_SEL | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt8_ick = {
+ .name = "gpt8_ick",
+ .prcmid = PRCM_GPT8,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt8_fck = {
+ .name = "gpt8_fck",
+ .prcmid = PRCM_GPT8,
+ .parent = &sys_ck, /* Can be sys_32k_ck too */
+ .rate = S_OSC,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | SRC_SEL | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt9_ick = {
+ .name = "gpt9_ick",
+ .prcmid = PRCM_GPT9,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP343X | I_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk gpt9_fck = {
+ .name = "gpt9_fck",
+ .prcmid = PRCM_GPT9,
+ .parent = &sys_ck, /* Can be sys_32k_ck too */
+ .rate = S_OSC,
+ .flags = CLOCK_IN_OMAP343X | F_CLK | SRC_SEL | POWER_ON_REQUIRED,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk sr1_fck = {
+ .name = "sr1_fck",
+ .prcmid = PRCM_SR1,
+ .parent = &sys_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+static struct clk sr2_fck = {
+ .name = "sr2_fck",
+ .prcmid = PRCM_SR2,
+ .parent = &sys_ck,
+ .flags = CLOCK_IN_OMAP343X | F_CLK,
+ .recalc = &omap3_followparent_recalc,
+};
+
+/* This node is used to model the external mcbsp clock*/
+/* Rate of the clock is supposed to be set using clk_set_rate API*/
+static struct clk ext_mcbsp_ck = {
+ .name = "ext_mcbsp_ck",
+ .prcmid = PRCM_EXT_MCBSP_CLK,
+ .rate = S96M,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .recalc = &omap3_propagate_rate,
+};
+
+static struct clk virt_vdd1_prcm_set = {
+ .name = "virt_vdd1_prcm_set",
+ .flags = CLOCK_IN_OMAP343X | VIRTUAL_CLOCK | ALWAYS_ENABLED,
+ .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
+ .recalc = &omap3_table_recalc, /* sets are keyed on mpu rate */
+ .set_rate = &omap3_select_table_rate,
+ .round_rate = &omap3_round_to_table_rate,
+};
+
+static struct clk virt_vdd2_prcm_set = {
+ .name = "virt_vdd2_prcm_set",
+ .flags = CLOCK_IN_OMAP343X | VIRTUAL_CLOCK | ALWAYS_ENABLED,
+ .parent = &core_ck, /* Indexed by core speed, no parent */
+ .recalc = &omap3_table_recalc, /* sets are keyed on mpu rate */
+ .set_rate = &omap3_select_table_rate,
+ .round_rate = &omap3_round_to_table_rate,
+};
+
+static struct clk *onchip_clks[] = {
+ /* external root sources */
+ &sys_32k_ck,
+ &osc_ck,
+ &sys_ck,
+ &sys_alt_ck,
+ /* internal sources */
+ &core_ck,
+ &core_x2_ck,
+ &emul_core_alwon_ck,
+ &cm_96m_ck,
+ &func_96m_ck,
+ &dpll4_m3x2_ck,
+ &emul_per_alwon_ck,
+ &func_48m_ck,
+ &func_12m_ck,
+ &dss_tv_fck,
+ &sys_clkout1,
+ &sys_clkout2,
+ &l3_ck,
+ &gpmc_fck,
+ &l4_ck,
+ &rm_ck,
+ &dpll1_fck,
+ &dpll2_fck,
+ &mpu_ck,
+ &iva2_ck,
+ &usim_fck,
+ &usim_ick,
+ &usbhost2_fck,
+ &cpefuse_fck,
+ &ts_fck,
+ &sgx_fck,
+ &sgx_ick,
+ &hsusb_ick,
+ &sdrc_ick,
+ &pka_ick,
+ &aes2_ick,
+ &sha12_ick,
+ &des2_ick,
+ &aes1_ick,
+ &sha11_ick,
+ &des1_ick,
+ &rng1_ick,
+ &mcbsp1_fck,
+ &mcbsp1_ick,
+ &mcbsp5_fck,
+ &mcbsp5_ick,
+ &mmc1_fck,
+ &mmc1_ick,
+ &mmc2_fck,
+ &mmc2_ick,
+ &mmc3_fck,
+ &mmc3_ick,
+ &mspro_fck,
+ &mspro_ick,
+ &i2c1_fck,
+ &i2c1_ick,
+ &i2c2_fck,
+ &i2c2_ick,
+ &i2c3_fck,
+ &i2c3_ick,
+ &usbhost_ick,
+ &usbhost1_fck,
+ &usbtll_host_sar_fck,
+ &usbtll_ick,
+ &uart1_fck,
+ &uart1_ick,
+ &uart2_fck,
+ &uart2_ick,
+ &mcspi1_fck,
+ &mcspi1_ick,
+ &mcspi2_fck,
+ &mcspi2_ick,
+ &mcspi3_fck,
+ &mcspi3_ick,
+ &mcspi4_fck,
+ &mcspi4_ick,
+ &hdq_fck,
+ &hdq_ick,
+ &gpt10_fck,
+ &gpt10_ick,
+ &gpt11_fck,
+ &gpt11_ick,
+ &omapctrl_ick,
+ &mailboxes_ick,
+ &ssi_ick,
+ &ssi_ssr_sst_fck,
+ &dss1_fck,
+ &dss_96m_fck,
+ &dss2_fck,
+ &dss_ick,
+ &cam_fck,
+ &cam_ick,
+ &csi2_fck,
+ &gpt1_fck,
+ &gpt1_ick,
+ &sync_32k_fck,
+ &sync_32k_ick,
+ &wdt2_fck,
+ &wdt2_ick,
+ &gpio1_fck,
+ &gpio1_ick,
+ &gpt12_fck,
+ &gpt12_ick,
+ &wdt1_fck,
+ &wdt1_ick,
+ &mcbsp2_fck,
+ &mcbsp2_ick,
+ &mcbsp3_fck,
+ &mcbsp3_ick,
+ &mcbsp4_fck,
+ &mcbsp4_ick,
+ &uart3_fck,
+ &uart3_ick,
+ &wdt3_fck,
+ &wdt3_ick,
+ &gpio2_fck,
+ &gpio2_ick,
+ &gpio3_fck,
+ &gpio3_ick,
+ &gpio4_fck,
+ &gpio4_ick,
+ &gpio5_fck,
+ &gpio5_ick,
+ &gpio6_fck,
+ &gpio6_ick,
+ &gpt2_fck,
+ &gpt2_ick,
+ &gpt3_fck,
+ &gpt3_ick,
+ &gpt4_fck,
+ &gpt4_ick,
+ &gpt5_fck,
+ &gpt5_ick,
+ &gpt6_fck,
+ &gpt6_ick,
+ &gpt7_fck,
+ &gpt7_ick,
+ &gpt8_fck,
+ &gpt8_ick,
+ &gpt9_fck,
+ &gpt9_ick,
+ &sr1_fck,
+ &sr2_fck,
+ /* External mcbsp clock */
+ &ext_mcbsp_ck,
+ /* virtual group clock */
+ &virt_vdd1_prcm_set,
+ &virt_vdd2_prcm_set,
+};
+
+#endif
Index: git-latest5/include/asm-arm/arch-omap/clock.h
===================================================================
--- git-latest5.orig/include/asm-arm/arch-omap/clock.h 2008-02-29 12:50:13.281830348 +0530
+++ git-latest5/include/asm-arm/arch-omap/clock.h 2008-02-29 20:29:47.057287887 +0530
@@ -65,6 +65,9 @@
void (*init)(struct clk *);
int (*enable)(struct clk *);
void (*disable)(struct clk *);
+#if defined(CONFIG_OMAP3_PM)
+ __u32 prcmid;
+#endif
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
u8 fixed_div;
void __iomem *clksel_reg;
--
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