Adding definitions used in TI power management files Signed-off-by: Karthik Dasu <karthik-dp@xxxxxx> Acked-by: Richard Woodruff <r-woodruff2@xxxxxx> --- arch/arm/mach-omap2/ti-compat.h | 197 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 197 insertions(+) Index: git-latest5/arch/arm/mach-omap2/ti-compat.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ git-latest5/arch/arm/mach-omap2/ti-compat.h 2008-02-29 11:36:42.937491839 +0530 @@ -0,0 +1,209 @@ +/* + * linux/arch/arm/mach-omap2/ti-compat.h + * + * Header file definitions to maintain compatibility with TI power + * framework + * + * Copyright (C) 2008 Texas Instruments Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _TI_COMPAT_H_ +#define _TI_COMPAT_H_ + +#include <asm/arch/hardware.h> + +/* ! NOTE: this is _NOT_ OMAP3430_PRM_BASE */ +#define PRM_BASE (L4_WK_34XX_BASE + 0x6000) +/* ! NOTE: this is _not_ OMAP3430_CM_BASE */ +#define CM_BASE (L4_34XX_BASE + 0x4000) +#define SDRC_BASE OMAP343X_SDRC_BASE +#define IC_BASE OMAP34XX_IC_BASE +#define OMAP_CTRL_BASE OMAP343X_CTRL_BASE + +#undef OMAP_TIMER32K_BASE +#define OMAP_TIMER32K_BASE IO_ADDRESS(OMAP2_32KSYNCT_BASE) + +/* MPU INTC registers */ +#define IC_REG32_34XX(offset) __REG32(IC_BASE + (offset)) +#define INTC_MIR_0 IC_REG32_34XX(0x084) +#define INTC_MIR_1 IC_REG32_34XX(0x0A4) +#define INTC_MIR_2 IC_REG32_34XX(0x0C4) +#define INTC_MIR_SET_0 IC_REG32_34XX(0x08C) +#define INTC_MIR_SET_1 IC_REG32_34XX(0x0AC) +#define INTC_MIR_SET_2 IC_REG32_34XX(0x0CC) +#define INTC_MIR_CLEAR_0 IC_REG32_34XX(0x094) +#define INTC_MIR_CLEAR_1 IC_REG32_34XX(0x0B4) +#define INTC_MIR_CLEAR_2 IC_REG32_34XX(0x0D4) +#define INTCPS_SYSCONFIG IC_REG32_34XX(0x010) +#define INTCPS_PROTECTION IC_REG32_34XX(0x04C) +#define INTCPS_IDLE IC_REG32_34XX(0x050) +#define INTCPS_THRESHOLD IC_REG32_34XX(0x068) +#define INTCPS_PENDING_IRQ0 IC_REG32_34XX(0x098) +#define INTCPS_PENDING_IRQ1 IC_REG32_34XX(0x0B8) +#define INTCPS_PENDING_IRQ2 IC_REG32_34XX(0x0D8) + +/* SDRC Register access */ +#define SDRC_REG32_34XX(offset) __REG32(SDRC_BASE + (offset)) +#define SDRC_PWR SDRC_REG32_34XX(0x70) +#define SDRC_CS_CFG SDRC_REG32_34XX(0x40) +#define SDRC_SYS_CONFIG SDRC_REG32_34XX(0x10) +#define SDRC_ERR_TYPE SDRC_REG32_34XX(0x4C) +#define SDRC_SHARING SDRC_REG32_34XX(0x44) +#define SDRC_DLL_A_CTRL SDRC_REG32_34XX(0x60) +#define SDRC_MCFG_0 SDRC_REG32_34XX(0x80) +#define SDRC_MR0 SDRC_REG32_34XX(0x84) +#define SDRC_ACTIM_CTRL_A_0 SDRC_REG32_34XX(0x9C) +#define SDRC_ACTIM_CTRL_B_0 SDRC_REG32_34XX(0xA0) +#define SDRC_RFR_CTRL_0 SDRC_REG32_34XX(0xA4) +#define SDRC_MCFG_1 SDRC_REG32_34XX(0xB0) +#define SDRC_MR1 SDRC_REG32_34XX(0xB4) +#define SDRC_ACTIM_CTRL_A_1 SDRC_REG32_34XX(0xC4) +#define SDRC_ACTIM_CTRL_B_1 SDRC_REG32_34XX(0xC8) +#define SDRC_RFR_CTRL_1 SDRC_REG32_34XX(0xD4) + +/* IO CONFIG */ +#define CONTROL_REG32_34XX(offset) __REG32(OMAP_CTRL_BASE + (offset)) +#define SCRATCHPAD_BASE CONTROL_REG32_34XX(0x910) +#define SCRATCHPAD_ROM_BASE CONTROL_REG32_34XX(0x860) +#define OMAP2_CONTROL_STATUS (OMAP_CTRL_BASE + 0x2f0) +#define CONTROL_SYSCONFIG CONTROL_REG32_34XX(0x010) +#define OMAP2_CONTROL_DEVCONF0 CONTROL_REG32_34XX(0x274) +#define OMAP2_CONTROL_DEVCONF1 CONTROL_REG32_34XX(0x2D8) +#define CONTROL_IVA2_BOOTMOD CONTROL_REG32_34XX(0x404) +#define CONTROL_IVA2_BOOTADDR CONTROL_REG32_34XX(0x400) +#define CONTROL_PADCONF_SYS_NIRQ CONTROL_REG32_34XX(0x1E0) +#define OMAP2_CONTROL_PBIAS_1 CONTROL_REG32_34XX(0x520) +#define CONTROL_PADCONF_MCBSP CONTROL_REG32_34XX(0x168) +#define CONTROL_PADCONF_UART3_CTS CONTROL_REG32_34XX(0x16A) +#define CONTROL_PADCONF_UART3_RX CONTROL_REG32_34XX(0x16C) +#define CONTROL_PADCONF_UART3_TX CONTROL_REG32_34XX(0x170) +#define CONTROL_PADCONF_UART1_TX CONTROL_REG32_34XX(0x17C) +#define CONTROL_PADCONF_UART1_CTS CONTROL_REG32_34XX(0x180) +#define CONTROL_PADCONF_OFF CONTROL_REG32_34XX(0x270) +#define CONTROL_GENERAL_PURPOSE_STATUS CONTROL_REG32_34XX(0x2F4) +#define CONTROL_MEM_DFTRW0 CONTROL_REG32_34XX(0x278) +#define CONTROL_MEM_DFTRW1 CONTROL_REG32_34XX(0x27C) +#define CONTROL_MSUSPENDMUX_0 CONTROL_REG32_34XX(0x290) +#define CONTROL_MSUSPENDMUX_1 CONTROL_REG32_34XX(0x294) +#define CONTROL_MSUSPENDMUX_2 CONTROL_REG32_34XX(0x298) +#define CONTROL_MSUSPENDMUX_3 CONTROL_REG32_34XX(0x29C) +#define CONTROL_MSUSPENDMUX_4 CONTROL_REG32_34XX(0x2A0) +#define CONTROL_MSUSPENDMUX_5 CONTROL_REG32_34XX(0x2A4) +#define CONTROL_SEC_CTRL CONTROL_REG32_34XX(0x2B0) +#define CONTROL_CSIRXFE CONTROL_REG32_34XX(0x2DC) +#define CONTROL_DEBOBS_0 CONTROL_REG32_34XX(0x420) +#define CONTROL_DEBOBS_1 CONTROL_REG32_34XX(0x424) +#define CONTROL_DEBOBS_2 CONTROL_REG32_34XX(0x428) +#define CONTROL_DEBOBS_3 CONTROL_REG32_34XX(0x42C) +#define CONTROL_DEBOBS_4 CONTROL_REG32_34XX(0x430) +#define CONTROL_DEBOBS_5 CONTROL_REG32_34XX(0x434) +#define CONTROL_DEBOBS_6 CONTROL_REG32_34XX(0x438) +#define CONTROL_DEBOBS_7 CONTROL_REG32_34XX(0x43C) +#define CONTROL_DEBOBS_8 CONTROL_REG32_34XX(0x440) +#define CONTROL_PROG_IO0 CONTROL_REG32_34XX(0x444) +#define CONTROL_PROG_IO1 CONTROL_REG32_34XX(0x448) +#define CONTROL_DSS_DPLL_SPREADING CONTROL_REG32_34XX(0x450) +#define CONTROL_CORE_DPLL_SPREADING CONTROL_REG32_34XX(0x454) +#define CONTROL_PER_DPLL_SPREADING CONTROL_REG32_34XX(0x458) +#define CONTROL_USBHOST_DPLL_SPREADING CONTROL_REG32_34XX(0x45C) +#define CONTROL_TEMP_SENSOR CONTROL_REG32_34XX(0x524) +#define CONTROL_SRAMLDO4 CONTROL_REG32_34XX(0x528) +#define CONTROL_SRAMLDO5 CONTROL_REG32_34XX(0x52C) +#define CONTROL_CSI CONTROL_REG32_34XX(0x530) +#define CONTROL_SCALABLE_OMAP_OCP CONTROL_REG32_34XX(0x534) +#define CONTROL_SCALABLE_OMAP_STATUS CONTROL_REG32_34XX(0x44C) +#define CONTROL_PADCONF_SYS_OFF_MODE CONTROL_REG32_34XX(0xA18) +#define CONTROL_PADCONF_SYS_NRESWARM CONTROL_REG32_34XX(0xA08) + +/* IO_PAD bit masks */ +#define IO_PAD_MUXMODE0 0x0 +#define IO_PAD_MUXMODE1 0x1 +#define IO_PAD_MUXMODE2 0x2 +#define IO_PAD_MUXMODE3 0x3 +#define IO_PAD_MUXMODE4 0x4 +#define IO_PAD_MUXMODE5 0x5 +#define IO_PAD_MUXMODE6 0x6 +#define IO_PAD_MUXMODE7 0x7 +#define IO_PAD_PULLUDENABLE 0x8 +#define IO_PAD_PULLTYPESELECT 0x10 +#define IO_PAD_INPUTENABLE 0x100 +#define IO_PAD_OFFENABLE 0x200 +#define IO_PAD_OFFOUTENABLE 0x400 +#define IO_PAD_OFFOUTVALUE 0x800 +#define IO_PAD_OFFPULLUDENABLE 0x1000 +#define IO_PAD_OFFPULLTYPESELECT 0x2000 +#define IO_PAD_WAKEUPENABLE 0x4000 +#define IO_PAD_WAKEUPEVENT 0x8000 +#define IO_PAD_HIGH_SHIFT 0x10 + +/* GPMC registers */ +#define GPMC_BASE OMAP34XX_GPMC_BASE +#define GPMC_REG32_34XX(offset) __REG32(GPMC_BASE + (offset)) +#define GPMC_SYS_CONFIG GPMC_REG32_34XX(0x10) +#define GPMC_IRQ_ENABLE GPMC_REG32_34XX(0x1C) +#define GPMC_TIMEOUT_CONTROL GPMC_REG32_34XX(0x40) +#define GPMC_CFG GPMC_REG32_34XX(0x50) +#define GPMC_PREFETCH_CONFIG_1 GPMC_REG32_34XX(0x1E0) +#define GPMC_PREFETCH_CONFIG_2 GPMC_REG32_34XX(0x1E4) +#define GPMC_PREFETCH_CTRL GPMC_REG32_34XX(0x1EC) +#define GPMC_CONFIG1_0 GPMC_REG32_34XX(0x60) +#define GPMC_CONFIG1_1 GPMC_REG32_34XX(0x90) +#define GPMC_CONFIG1_2 GPMC_REG32_34XX(0xC0) +#define GPMC_CONFIG1_3 GPMC_REG32_34XX(0xF0) +#define GPMC_CONFIG1_4 GPMC_REG32_34XX(0x120) +#define GPMC_CONFIG1_5 GPMC_REG32_34XX(0x150) +#define GPMC_CONFIG1_6 GPMC_REG32_34XX(0x180) +#define GPMC_CONFIG1_7 GPMC_REG32_34XX(0x1B0) +#define GPMC_CONFIG2_0 GPMC_REG32_34XX(0x64) +#define GPMC_CONFIG2_1 GPMC_REG32_34XX(0x94) +#define GPMC_CONFIG2_2 GPMC_REG32_34XX(0xC4) +#define GPMC_CONFIG2_3 GPMC_REG32_34XX(0xF4) +#define GPMC_CONFIG2_4 GPMC_REG32_34XX(0x124) +#define GPMC_CONFIG2_5 GPMC_REG32_34XX(0x154) +#define GPMC_CONFIG2_6 GPMC_REG32_34XX(0x184) +#define GPMC_CONFIG2_7 GPMC_REG32_34XX(0x1B4) +#define GPMC_CONFIG3_0 GPMC_REG32_34XX(0x68) +#define GPMC_CONFIG3_1 GPMC_REG32_34XX(0x98) +#define GPMC_CONFIG3_2 GPMC_REG32_34XX(0xC8) +#define GPMC_CONFIG3_3 GPMC_REG32_34XX(0xF8) +#define GPMC_CONFIG3_4 GPMC_REG32_34XX(0x128) +#define GPMC_CONFIG3_5 GPMC_REG32_34XX(0x158) +#define GPMC_CONFIG3_6 GPMC_REG32_34XX(0x188) +#define GPMC_CONFIG3_7 GPMC_REG32_34XX(0x1B8) +#define GPMC_CONFIG4_0 GPMC_REG32_34XX(0x6C) +#define GPMC_CONFIG4_1 GPMC_REG32_34XX(0x9C) +#define GPMC_CONFIG4_2 GPMC_REG32_34XX(0xCC) +#define GPMC_CONFIG4_3 GPMC_REG32_34XX(0xFC) +#define GPMC_CONFIG4_4 GPMC_REG32_34XX(0x12C) +#define GPMC_CONFIG4_5 GPMC_REG32_34XX(0x15C) +#define GPMC_CONFIG4_6 GPMC_REG32_34XX(0x18C) +#define GPMC_CONFIG4_7 GPMC_REG32_34XX(0x1BC) +#define GPMC_CONFIG5_0 GPMC_REG32_34XX(0x70) +#define GPMC_CONFIG5_1 GPMC_REG32_34XX(0xA0) +#define GPMC_CONFIG5_2 GPMC_REG32_34XX(0xD0) +#define GPMC_CONFIG5_3 GPMC_REG32_34XX(0x100) +#define GPMC_CONFIG5_4 GPMC_REG32_34XX(0x130) +#define GPMC_CONFIG5_5 GPMC_REG32_34XX(0x160) +#define GPMC_CONFIG5_6 GPMC_REG32_34XX(0x190) +#define GPMC_CONFIG5_7 GPMC_REG32_34XX(0x1C0) +#define GPMC_CONFIG6_0 GPMC_REG32_34XX(0x74) +#define GPMC_CONFIG6_1 GPMC_REG32_34XX(0xA4) +#define GPMC_CONFIG6_2 GPMC_REG32_34XX(0xD4) +#define GPMC_CONFIG6_3 GPMC_REG32_34XX(0x104) +#define GPMC_CONFIG6_4 GPMC_REG32_34XX(0x134) +#define GPMC_CONFIG6_5 GPMC_REG32_34XX(0x164) +#define GPMC_CONFIG6_6 GPMC_REG32_34XX(0x194) +#define GPMC_CONFIG6_7 GPMC_REG32_34XX(0x1C4) +#define GPMC_CONFIG7_0 GPMC_REG32_34XX(0x78) +#define GPMC_CONFIG7_1 GPMC_REG32_34XX(0xA8) +#define GPMC_CONFIG7_2 GPMC_REG32_34XX(0xD8) +#define GPMC_CONFIG7_3 GPMC_REG32_34XX(0x108) +#define GPMC_CONFIG7_4 GPMC_REG32_34XX(0x138) +#define GPMC_CONFIG7_5 GPMC_REG32_34XX(0x168) +#define GPMC_CONFIG7_6 GPMC_REG32_34XX(0x198) +#define GPMC_CONFIG7_7 GPMC_REG32_34XX(0x1C8) + +#endif -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
