* Nishanth Menon <menon.nishanth@xxxxxxxxx> [080124 17:20]:
> Tony,
> Tony Lindgren mentioned the following on 1/24/2008 4:17 PM:
>> * Klaus.K Pedersen (Nokia-M/Helsinki) <klaus.k.pedersen@xxxxxxxxx> [080124 13:19]:
>>
>>> On Wed, 2008-01-23 at 16:53 -0800, ext Tony Lindgren wrote:
>>>
>>>> From: Gadiyar, Anand <gadiyar@xxxxxx>
>>>>
>>>> This patch adds pinmux support for OMAP3.
>>>>
>>> ....
>>>
>>>> +
>>>> +/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
>>>> +MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8, 3, 1, 1, 0,
>>>> + 0, 0, 0, 1, 1, 0)
>>>>
>>> And you would spot the error in this one right away:
>>>
>>> MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8, 3, 1, 1, 0,
>>> 0, 0, 0, 1, 1, 0)
>>>
>>> which would become:
>>>
>>> MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8, 3, OUTPUT, OFF_INPUT_PULL_H)
>>>
>>
>> This sounds like a good way to group the pin options to me. We
>> could also pass the active state flags to omap_cfg_reg() as some may
>> depend on devices connected.
>>
>> Can anybody see cases where Klaus' grouping would not work?
>>
> Dunno if I missed some mail in this thread, but the obvious occured: Have
> we considered having more readable macros? I mean modes are only 1-7
> (3bits- and give one more for safe), then add the others
> #define MODE(x) ((x)&0xF)
> #define PULL_EN (0x1<<5)
> #define PULL_DIS (0x0<<5)
> #define PULL_UP (0x1<<6)
> #define PULL_DOWN (0x0<<6)
> #define OUTPUT (0x1<<7)
> #define INPUT (0x0<<7)
> etc.. 1 bit per field. use 16 bit to store the vals (just like the regs)
> and Thus,
>
> MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8, 3, 1, 1, 0,
> 0, 0, 0, 1, 1, 0)
> becomes:
> MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8, 3, OUTPUT, OFF_INPUT_PULL_H)
> becomes:
> MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8, MODE(3)|OUTPUT|PULL_DIS|WAKEUP_EN)
>
> All platforms can live with that rt? the pin_config structure gets simpler(and less of a nightmare) and portable :D
Well originally the format was intended to be easy to compare against
the 1510 TRM tables. If we can group the sensible options, things will
simpler.
> struct pin_config {
> char *name;
> unsigned char busy;
> unsigned char debug;
>
> const unsigned int mux_reg;
> const unsigned short mux_def;
> }
> And one more thing (maybe I am wrong): I think i still see that we are driving mux common for all platforms on the same silicon. as we get more boards using and "misusing" the mux concept, I think at some point we'd need to refactor mux driver to allow omap_mux_register be called platform specific. shrug.. just an old opinion..
Passing the configuration option to omap_cfg_reg() would help
with board specific configurations or what do you think? Then the
muxing just becomes selecting the pinout from the mux table, and
configuring it as desired, something like:
omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT, MUX_INPUT | OFF_NONE);
and to avoid messing with omap1 mux tables, we can let them be
as they are for now, and just pass them
omap_cfg_reg(XY_15XX_SOMPIN, MUX_DEFAULT);
BTW, I've refreshed the mux clean-up and omap_ctrl_reg patches,
and pushed them. So that only leaves Anand's 3430 mux patch unapplied.
I've refreshed that one too for reference, see below.
Regards,
Tony
>From 649f8dc6341f3b6f0f2adbd410c38618cd7f6834 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@xxxxxxxxxxx>
Date: Thu, 24 Jan 2008 17:18:32 -0800
Subject: [PATCH] ARM: OMAP2: Add pinmux support for OMAP3430, take3
From: From: Gadiyar, Anand <gadiyar@xxxxxx>
This patch adds pinmux support for OMAP3.
Signed-off-by: Anand Gadiyar <gadiyar@xxxxxx>
Acked-by: Vikram Pandita <vikram.pandita@xxxxxx>
Signed-off-by: Tony Lindgren <tony@xxxxxxxxxxx>
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index fa86281..2ddd945 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,7 +1,7 @@
/*
* linux/arch/arm/mach-omap2/mux.c
*
- * OMAP2 pin multiplexing configurations
+ * OMAP2 and OMAP3 pin multiplexing configurations
*
* Copyright (C) 2004 - 2008 Texas Instruments Inc.
* Copyright (C) 2003 - 2008 Nokia Corporation
@@ -219,9 +219,88 @@ MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
#define OMAP24XX_PINS_SZ 0
#endif /* CONFIG_ARCH_OMAP24XX */
+#ifdef CONFIG_ARCH_OMAP34XX
+static struct pin_config __initdata_or_module omap34xx_pins[] = {
+/*
+ * description mux mux pull pull inp
+ * offset mode ena type ena
+ *
+ * off off off off off wkup
+ * ena outen outval pullen pulltyp en
+ */
+
+/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
+MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8, 3, 1, 1, 0,
+ 0, 0, 0, 1, 1, 0)
+MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+
+/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
+MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2, 3, 1, 1, 0,
+ 0, 0, 0, 1, 1, 0)
+MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de, 3, 0, 0, 1,
+ 0, 0, 0, 0, 0, 0)
+};
+
+#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
+
+#else
+#define omap34xx_pins NULL
+#define OMAP34XX_PINS_SZ 0
+#endif /* CONFIG_ARCH_OMAP34XX */
+
#define OMAP24XX_PULL_ENA (1 << 3)
#define OMAP24XX_PULL_UP (1 << 4)
+#define OMAP3_INPUT_EN (1 << 8)
+#define OMAP3_OFF_EN (1 << 9)
+#define OMAP3_OFFOUT_EN (1 << 10)
+#define OMAP3_OFFOUT_VAL (1 << 11)
+#define OMAP3_OFF_PULL_EN (1 << 12)
+#define OMAP3_OFF_PULL_UP (1 << 13)
+#define OMAP3_WAKEUP_EN (1 << 14)
+
+
#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
{
@@ -270,6 +349,44 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
#define omap24xx_cfg_reg 0
#endif
+#ifdef CONFIG_ARCH_OMAP34XX
+/* REVISIT: Convert this code to use ctrl_{read,write}_reg */
+int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg)
+{
+ static DEFINE_SPINLOCK(mux_spin_lock);
+ unsigned long flags;
+ u8 reg = 0;
+
+ spin_lock_irqsave(&mux_spin_lock, flags);
+ reg |= cfg->mask & 0x7;
+ if (cfg->pull_val)
+ reg |= OMAP24XX_PULL_ENA;
+ if(cfg->pu_pd_val)
+ reg |= OMAP24XX_PULL_UP;
+ if (cfg->input_en_val)
+ reg |= OMAP3_INPUT_EN;
+ if (cfg->offenable)
+ reg |= OMAP3_OFF_EN;
+ if (cfg->offoutenable)
+ reg |= OMAP3_OFFOUT_EN;
+ if (cfg->offoutvalue)
+ reg |= OMAP3_OFFOUT_VAL;
+ if (cfg->offpulludenable)
+ reg |= OMAP3_OFF_PULL_EN;
+ if (cfg->offpulltypeselect)
+ reg |= OMAP3_OFF_PULL_UP;
+ if (cfg->wakeupenable)
+ reg |= OMAP3_WAKEUP_EN;
+ omap2_cfg_debug(cfg, reg);
+ omap_ctrl_writew(reg, cfg->mux_reg);
+ spin_unlock_irqrestore(&mux_spin_lock, flags);
+
+ return 0;
+}
+#else
+#define omap34xx_cfg_reg 0
+#endif
+
int __init omap2_mux_init(void)
{
if (cpu_is_omap24xx()) {
@@ -278,6 +395,12 @@ int __init omap2_mux_init(void)
arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
}
+ if (cpu_is_omap34xx()) {
+ arch_mux_cfg.pins = omap34xx_pins;
+ arch_mux_cfg.size = OMAP24XX_PINS_SZ;
+ arch_mux_cfg.cfg_reg = omap34xx_cfg_reg;
+ }
+
return omap_mux_register(&arch_mux_cfg);
}
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index b8088d9..daa051d 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -125,6 +125,30 @@
.pu_pd_val = pull_mode, \
},
+#define MUX_CFG_34XX(desc, reg_offset, mode, \
+ pull_en, pull_mode, \
+ input_en, \
+ off_en, \
+ offout_en, \
+ offout_val, \
+ offpullud_en, \
+ offpull_typesel, \
+ wakeup_en) \
+{ \
+ .name = desc, \
+ .debug = 0, \
+ .mux_reg = reg_offset, \
+ .mask = mode, \
+ .pull_val = pull_en, \
+ .pu_pd_val = pull_mode, \
+ .input_en_val = input_en, \
+ .offenable = off_en, \
+ .offoutenable = offout_en, \
+ .offoutvalue = offout_val, \
+ .offpulludenable = offpullud_en, \
+ .offpulltypeselect = offpull_typesel, \
+ .wakeupenable = wakeup_en \
+},
#define PULL_DISABLED 0
#define PULL_ENABLED 1
@@ -150,6 +174,14 @@ struct pin_config {
const char *pu_pd_name;
const unsigned int pu_pd_reg;
const unsigned char pu_pd_val;
+
+ const unsigned input_en_val:1;
+ const unsigned offenable:1;
+ const unsigned offoutenable:1;
+ const unsigned offoutvalue:1;
+ const unsigned offpulludenable:1;
+ const unsigned offpulltypeselect:1;
+ const unsigned wakeupenable:1;
};
enum omap730_index {
@@ -590,6 +622,39 @@ enum omap24xx_index {
AD16_2430_MCBSP2_CLX_OFF,
AE13_2430_MCBSP2_DX_OFF,
AD13_2430_MCBSP2_DR_OFF,
+
+};
+
+enum omap34xx_index {
+
+ /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
+ Y9_3430_USB1HS_PHY_STP,
+ Y8_3430_USB1HS_PHY_CLK,
+ W13_3430_USB1HS_PHY_DATA0,
+ W12_3430_USB1HS_PHY_DATA1,
+ W11_3430_USB1HS_PHY_DATA2,
+ Y13_3430_USB1HS_PHY_DATA7,
+ W9_3430_USB1HS_PHY_DATA4,
+ Y12_3430_USB1HS_PHY_DATA5,
+ W8_3430_USB1HS_PHY_DATA6,
+ Y11_3430_USB1HS_PHY_DATA3,
+ AA14_3430_USB1HS_PHY_DIR,
+ AA11_3430_USB1HS_PHY_NXT,
+
+ /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
+ AA8_3430_USB2HS_PHY_CLK,
+ AA10_3430_USB2HS_PHY_STP,
+ AA9_3430_USB2HS_PHY_DIR,
+ AB11_3430_USB2HS_PHY_NXT,
+ AB10_3430_USB2HS_PHY_DATA0,
+ AB9_3430_USB2HS_PHY_DATA1,
+ W3_3430_USB2HS_PHY_DATA2,
+ T2_3430_USB2HS_PHY_DATA7,
+ T3_3430_USB2HS_PHY_DATA4,
+ R3_3430_USB2HS_PHY_DATA5,
+ R4_3430_USB2HS_PHY_DATA6,
+ T4_3430_USB2HS_PHY_DATA3,
+
};
struct omap_mux_cfg {
