On Tue, Jun 17, 2008 at 01:09:19AM +0200, Andi Kleen wrote:
> Cliff Wickman wrote:
> > From: Cliff Wickman <cpw@xxxxxxx>
> >
> > Clear caches between numademo runs - ia64 style.
> > Use the fc instruction to clear cache.
> > Assuming 128-byte cache lines.
> >
> > Look right?
>
> Would be better to discover the cache line size too like x86 does
> (not sure how though)
> or use 32bytes because that is guaranteed by the architecture.
There is no instruction to tell you cache line size; you'd have to
ask to OS. But L3/L2 cache lines are always 128 on Itanium2 (64 on
Merced).
To be safe we could stride at 64. There would be a bad performance hit
for the second flush of each line, as a broadcast would be done to
all caches. But that's probably not an issue for numademo's use.
> And not sure the manual alignment is really needed.
I suppose not, as the possible extra cache line flush would not be an issue.
So how about:
Index: numactl-dev/clearcache.c
===================================================================
--- numactl-dev.orig/clearcache.c
+++ numactl-dev/clearcache.c
@@ -63,6 +63,13 @@ void clearcache(unsigned char *mem, unsi
cl = ((cl >> 8) & 0xff) * 8;
for (i = 0; i < size; i += cl)
asm("clflush %0" :: "m" (mem[i]));
+#elif defined(__ia64__)
+ unsigned long cl, endcl;
+ // flush probable 128 byte cache lines (but possibly 64 bytes)
+ cl = (unsigned long)mem;
+ endcl = (unsigned long)(mem + (size-1));
+ for (; cl <= endcl; cl += 64)
+ asm ("fc %0" :: "r"(cl) : "memory" );
#else
#warning "Consider adding a clearcache implementation for your architecture"
fallback_clearcache();
-Cliff
>
>
> >
> > Signed-off-by: Cliff Wickman <cpw@xxxxxxx>
> > ---
> > clearcache.c | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > Index: numactl-dev/clearcache.c
> > ===================================================================
> > --- numactl-dev.orig/clearcache.c
> > +++ numactl-dev/clearcache.c
> > @@ -63,6 +63,13 @@ void clearcache(unsigned char *mem, unsi
> > cl = ((cl >> 8) & 0xff) * 8;
> > for (i = 0; i < size; i += cl)
> > asm("clflush %0" :: "m" (mem[i]));
> > +#elif defined(__ia64__)
> > + unsigned long cl, endcl;
> > + // flush 128-byte cache lines
> > + cl = ((unsigned long)mem >> 7) << 7;
> > + endcl = ((unsigned long)(mem + (size-1)) >> 7) << 7;
> > + for (; cl <= endcl; cl += 128)
> > + asm ("fc %0" :: "r"(cl) : "memory" );
> > #else
> > #warning "Consider adding a clearcache implementation for your architecture"
> > fallback_clearcache();
> >
>
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--
Cliff Wickman
Silicon Graphics, Inc.
cpw@xxxxxxx
(651) 683-3824
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