On 9/23/2015 12:27 AM, Bart Van Assche wrote:
On 09/17/2015 02:42 AM, Sagi Grimberg wrote:
+static int
+mlx5_alloc_priv_descs(struct ib_device *device,
+ struct mlx5_ib_mr *mr,
+ int ndescs,
+ int desc_size)
+{
+ int size = ndescs * desc_size;
+
+ mr->descs = dma_alloc_coherent(device->dma_device, size,
+ &mr->desc_map, GFP_KERNEL);
+ if (!mr->descs)
+ return -ENOMEM;
+
+ return 0;
+}
Would it be possible to clarify the choice for coherent memory ?
No specific reason. I was just copying alloc_fastreg_page_list logic.
Would performance be better if non-coherent memory would be used and if memory
would be synced after initialization of desc_map has finished ?
It probably would I assume. I'll change that.
Thanks!
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