On Fri, Jan 23, 2004 at 11:32:41PM -0800, David S. Miller wrote:
> Maybe keep a shorter note about the bit changed meaning in later models
> just to document the issues.
>
> We can "document it" by having the setting of this bit be protected by
> chip version numbers. I'd happily accept such a patch.
Re DMA_RWCTRL_ASSERT_ALL_BE changes
This is the second part of the patch.
Enable PCI-X/32-bit bug workaround which is present
in bcm570[34] A3 (and later) chip revs.
bcm570[34] A0/A1/A2 are SOL. Move the cards to PCI slot until
someone figures out 64-bit PCI Host bus controllers are safe too.
thanks,
grant
Index: drivers/net/tg3.c
===================================================================
RCS file: /var/cvs/linux-2.6/drivers/net/tg3.c,v
retrieving revision 1.14
diff -u -p -r1.14 tg3.c
--- a/drivers/net/tg3.c 16 Mar 2004 15:40:18 -0000 1.14
+++ b/drivers/net/tg3.c 18 Mar 2004 05:56:09 -0000
@@ -7308,14 +7308,40 @@ static int __devinit tg3_test_dma(struct
* to streamable DMA memory with not all the byte
* enables turned on. This is an error on several
* RISC PCI controllers, in particular sparc64.
- *
- * On 5703/5704 chips, this bit has been reassigned
- * a different meaning. In particular, it is used
- * on those chips to enable a PCI-X workaround.
*/
tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
+ } else if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
+ (tp->tg3_flags & TG3_FLAG_PCIX_MODE) ) {
+ /*
+ * programmers guide (57XX-PG101-R) says:
+ * "Bit 23 - PCI-X DMA Write Single Disconnect Fix
+ * (BCM5703 A3 and later, BCM5704 A3 and later)
+ * "Setting this bit to 1 fixes the following hardware
+ * errata: DMA write single cycle disconnect followed by
+ * a DMA Read split completion, followed by the continuation
+ * of DMA write causes data duplication."
+ *
+ * See "E7_5703CA2_419: Data Corruption After a Sequence
+ * of Unique PCI-X, 32-bit Transactions"
+ *
+ * Even though the bug only occurs with PCI-X 32-bit
+ * transactions, we don't test TG3_FLAG_PCI_32BIT above
+ * because we decided wierd 64-bit PCI Bus controller
+ * *might* not assert REQ64# for all transactions (ie only
+ * send 32-bits). Someone might later determine we were
+ * on crack and test for PCI_32BIT above as well.
+ */
+ if (GET_METAL_REV(tp->pci_chip_rev_id) > METAL_REV_B2) {
+ tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
+ } else {
+ /*
+ * A0/A1/A2 have no workaround. :^(
+ */
+ printk(KERN_WARNING PFX "%s: WARNING - See Errata 5703CA2_419 for rare data corruption.\n", tp->dev->name);
+ printk(KERN_WARNING PFX "%s: Try a 64-bit slot or PCI slot (not PCI-X)\n", tp->dev->name);
+ }
}
-
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
#if 0
-
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