> I recall from the profiling that PPC interrupt handling showed up > clearly as the biggest time consumer. If the interrupt controller > is even slightly different between your test machines, that would > explain a lot. > > I wish some PPC expert would comment on why the PPC interrupt code > consumes so much time. So, with help from Gabriel Paubert, we found the bottleneck! On the MVME2600, the PCI bus latency timer was set to 0. In principle, this register is set by the firmware, and Linux doesn't touch it. On the x86, pcibios_set_master() would have fixed this up; there is a comment * If we set up a device for bus mastering, we need to check the latency * timer as certain crappy BIOSes forget to set it properly. The PowerPC doesn't do this, and perhaps there is a reason that Motorola calls their firmware package "PPCBug." :-) I have the impression that a latency setting of 0 effectively prohibits burst-mode transfers on the PCI bus. For latency = 128: MTU [bytes] Non-zero-copy [10^6 bytes/s] Zero-copy [10^6 bytes/s] 1500 15.78 30.27 9000 18.74 36.19 16000 18.82 37.18 For latency = 255: MTU [bytes] Non-zero-copy [10^6 bytes/s] Zero-copy [10^6 bytes/s] 1500 16.21 40.79 9000 19.85 44.03 16000 20.00 44.23 This 40 MB/s is about the level of performance that I had expected from my "bicycle," and it should be sufficient for our application. Thanks again, -- Fred -- Fred Gray / Visiting Postdoctoral Researcher -- -- Department of Physics / University of California, Berkeley -- -- fegray@socrates.berkeley.edu / phone 510-642-4057 / fax 510-642-9811 -- - : send the line "unsubscribe linux-net" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
