Re: [RFC PATCH 0/3] Fix proposal for the Micron shallow erase issue

[Miquel Raynal <miquel.raynal@xxxxxxxxxxx>]

Hi Bean,

There are two technical questions below that I would like you to answer.

> >>> Also after power loss all flags in micron->writtenp are gone so the
> >>> micron_nand_avoid_shallow_erase will perform on all PEBs causing performance loss.  
> >>
> >> Yes, that's a performance hit we'll have to accept for now.
> >>  
> > 
> > This is quite severe issue, this is the best idea we came with to
> > limit performance hits.  
> 
> This will be an issue on devices which restarts quite often, what if we read OOB of middle 
> page of the block we are about to erase and if it has all 0xff the it means it is 
> partially programmed and needs the quirk. It's reading 64/128 bytes (depending on NAND 
> size) before every erase versus programming 8 pages on each PEB erase once per device restart.
> 
> Also I know by speaking with Micron that programming 0 in spare area is enough and 
> actually we should program 8 even/odd pages starting from middle of PEB. In case PEB has 
> 64 pages we should program OOB of page 31,33,35,37,39,41,43,45 or 32,34,36,38,40,42,44,46
> Can somebody from Micron confirm that?

So the questions are:

1/ What should we write exactly:
    -> the main area
    -> the OOB area
    -> both
   ?

2/ Shall we prefer writing 8 even/odd pages starting from:
    -> the beginning of the
    -> the middle of the block
    -> we do not care
   ?

Thanks,
Miquèl

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