On 28.02.20 04:12, Yoshio Furuyama wrote:
> Add support for new Kioxia products.
> The new Kioxia products support program load x4 command, and have
> HOLD_D bit which is equivalent to QE bit.
>
> Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@xxxxxxxxxx>
Reviewed-by: Frieder Schrempf <frieder.schrempf@xxxxxxxxxx>
> ---
> changelog[v2]:Split 2 patches.
>
> drivers/mtd/nand/spi/toshiba.c | 119 +++++++++++++++++++++++++++++++++++------
> 1 file changed, 103 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c
> index 700d86f..505f9f5 100644
> --- a/drivers/mtd/nand/spi/toshiba.c
> +++ b/drivers/mtd/nand/spi/toshiba.c
> @@ -19,6 +19,18 @@ static SPINAND_OP_VARIANTS(read_cache_variants,
> SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
> SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
>
> +static SPINAND_OP_VARIANTS(write_cache_x4_variants,
> + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
> + SPINAND_PROG_LOAD(true, 0, NULL, 0));
> +
> +static SPINAND_OP_VARIANTS(update_cache_x4_variants,
> + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
> + SPINAND_PROG_LOAD(false, 0, NULL, 0));
> +
> +/**
> + * Backward compatibility for 1st generation Serial NAND devices
> + * which don't support Quad Program Load operation.
> + */
> static SPINAND_OP_VARIANTS(write_cache_variants,
> SPINAND_PROG_LOAD(true, 0, NULL, 0));
>
> @@ -94,7 +106,7 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
> }
>
> static const struct spinand_info toshiba_spinand_table[] = {
> - /* 3.3V 1Gb */
> + /* 3.3V 1Gb (1st generation) */
> SPINAND_INFO("TC58CVG0S3HRAIG", 0xC2,
> NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
> NAND_ECCREQ(8, 512),
> @@ -104,7 +116,7 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
> 0,
> SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> tx58cxgxsxraix_ecc_get_status)),
> - /* 3.3V 2Gb */
> + /* 3.3V 2Gb (1st generation) */
> SPINAND_INFO("TC58CVG1S3HRAIG", 0xCB,
> NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
> NAND_ECCREQ(8, 512),
> @@ -114,7 +126,7 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
> 0,
> SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> tx58cxgxsxraix_ecc_get_status)),
> - /* 3.3V 4Gb */
> + /* 3.3V 4Gb (1st generation) */
> SPINAND_INFO("TC58CVG2S0HRAIG", 0xCD,
> NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
> NAND_ECCREQ(8, 512),
> @@ -124,17 +136,7 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
> 0,
> SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> tx58cxgxsxraix_ecc_get_status)),
> - /* 3.3V 4Gb */
> - SPINAND_INFO("TC58CVG2S0HRAIJ", 0xED,
> - NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
> - NAND_ECCREQ(8, 512),
> - SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> - &write_cache_variants,
> - &update_cache_variants),
> - 0,
> - SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> - tx58cxgxsxraix_ecc_get_status)),
> - /* 1.8V 1Gb */
> + /* 1.8V 1Gb (1st generation) */
> SPINAND_INFO("TC58CYG0S3HRAIG", 0xB2,
> NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
> NAND_ECCREQ(8, 512),
> @@ -144,7 +146,7 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
> 0,
> SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> tx58cxgxsxraix_ecc_get_status)),
> - /* 1.8V 2Gb */
> + /* 1.8V 2Gb (1st generation) */
> SPINAND_INFO("TC58CYG1S3HRAIG", 0xBB,
> NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
> NAND_ECCREQ(8, 512),
> @@ -154,7 +156,7 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
> 0,
> SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> tx58cxgxsxraix_ecc_get_status)),
> - /* 1.8V 4Gb */
> + /* 1.8V 4Gb (1st generation) */
> SPINAND_INFO("TC58CYG2S0HRAIG", 0xBD,
> NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
> NAND_ECCREQ(8, 512),
> @@ -164,6 +166,91 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
> 0,
> SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> tx58cxgxsxraix_ecc_get_status)),
> +
> + /*
> + * 2nd generation serial nand has HOLD_D which is equivalent to
> + * QE_BIT.
> + */
> + /* 3.3V 1Gb (2nd generation) */
> + SPINAND_INFO("TC58CVG0S3HRAIJ", 0xE2,
> + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_x4_variants,
> + &update_cache_x4_variants),
> + SPINAND_HAS_QE_BIT,
> + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> + tx58cxgxsxraix_ecc_get_status)),
> + /* 3.3V 2Gb (2nd generation) */
> + SPINAND_INFO("TC58CVG1S3HRAIJ", 0xEB,
> + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_x4_variants,
> + &update_cache_x4_variants),
> + SPINAND_HAS_QE_BIT,
> + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> + tx58cxgxsxraix_ecc_get_status)),
> + /* 3.3V 4Gb (2nd generation) */
> + SPINAND_INFO("TC58CVG2S0HRAIJ", 0xED,
> + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_x4_variants,
> + &update_cache_x4_variants),
> + SPINAND_HAS_QE_BIT,
> + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> + tx58cxgxsxraix_ecc_get_status)),
> + /* 3.3V 8Gb (2nd generation) */
> + SPINAND_INFO("TH58CVG3S0HRAIJ", 0xE4,
> + NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_x4_variants,
> + &update_cache_x4_variants),
> + SPINAND_HAS_QE_BIT,
> + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> + tx58cxgxsxraix_ecc_get_status)),
> + /* 1.8V 1Gb (2nd generation) */
> + SPINAND_INFO("TC58CYG0S3HRAIJ", 0xD2,
> + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_x4_variants,
> + &update_cache_x4_variants),
> + SPINAND_HAS_QE_BIT,
> + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> + tx58cxgxsxraix_ecc_get_status)),
> + /* 1.8V 2Gb (2nd generation) */
> + SPINAND_INFO("TC58CYG1S3HRAIJ", 0xDB,
> + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_x4_variants,
> + &update_cache_x4_variants),
> + SPINAND_HAS_QE_BIT,
> + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> + tx58cxgxsxraix_ecc_get_status)),
> + /* 1.8V 4Gb (2nd generation) */
> + SPINAND_INFO("TC58CYG2S0HRAIJ", 0xDD,
> + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_x4_variants,
> + &update_cache_x4_variants),
> + SPINAND_HAS_QE_BIT,
> + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> + tx58cxgxsxraix_ecc_get_status)),
> + /* 1.8V 8Gb (2nd generation) */
> + SPINAND_INFO("TH58CYG3S0HRAIJ", 0xD4,
> + NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_x4_variants,
> + &update_cache_x4_variants),
> + SPINAND_HAS_QE_BIT,
> + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
> + tx58cxgxsxraix_ecc_get_status)),
> };
>
> static int toshiba_spinand_detect(struct spinand_device *spinand)
>
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Re: [PATCH v2 2/2] mtd: spinand: toshiba: Support for new Kioxia Serial NAND
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- Subject: Re: [PATCH v2 2/2] mtd: spinand: toshiba: Support for new Kioxia Serial NAND
- From: Schrempf Frieder <frieder.schrempf@xxxxxxxxxx>
- Date: Mon, 2 Mar 2020 08:03:11 +0000
- Accept-language: de-DE, en-US
- Cc: "linux-mtd@xxxxxxxxxxxxxxxxxxx" <linux-mtd@xxxxxxxxxxxxxxxxxxx>, "linux-kernel@xxxxxxxxxxxxxxx" <linux-kernel@xxxxxxxxxxxxxxx>
- In-reply-to: <9080db5a16d0fae0b0e04245e8aacc774107222c.1582603241.git.ytc-mb-yfuruyama7@kioxia.com>
- References: <cover.1582603241.git.ytc-mb-yfuruyama7@kioxia.com> <9080db5a16d0fae0b0e04245e8aacc774107222c.1582603241.git.ytc-mb-yfuruyama7@kioxia.com>
- References:
- [PATCH v2 0/2] mtd: spinand: toshiba: Support for new Kioxia Serial NAND
- From: Yoshio Furuyama
- [PATCH v2 2/2] mtd: spinand: toshiba: Support for new Kioxia Serial NAND
- From: Yoshio Furuyama
- [PATCH v2 0/2] mtd: spinand: toshiba: Support for new Kioxia Serial NAND
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