From: Tudor Ambarus <tudor.ambarus@xxxxxxxxxxxxx> JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20, refers to this bit as "bit 1 of the status register 2". Rename the macro accordingly. Signed-off-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxxxxx> --- drivers/mtd/spi-nor/spi-nor.c | 10 +++++----- include/linux/mtd/spi-nor.h | 4 +--- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index eecbd161df25..1f7ccd80b8ed 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1026,7 +1026,7 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) * Write Status (01h) command is available just for the cases * in which the QE bit is described in SR2 at BIT(1). */ - sr_cr[1] = CR_QUAD_EN_SPAN; + sr_cr[1] = SR2_QUAD_EN_BIT1; } else { sr_cr[1] = 0; } @@ -2074,7 +2074,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) if (ret) return ret; - sr_cr[1] = CR_QUAD_EN_SPAN; + sr_cr[1] = SR2_QUAD_EN_BIT1; ret = spi_nor_write_sr(nor, sr_cr, 2); if (ret) @@ -2118,10 +2118,10 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor) if (ret) return ret; - if (sr_cr[1] & CR_QUAD_EN_SPAN) + if (sr_cr[1] & SR2_QUAD_EN_BIT1) return 0; - sr_cr[1] |= CR_QUAD_EN_SPAN; + sr_cr[1] |= SR2_QUAD_EN_BIT1; /* Keep the current value of the Status Register. */ ret = spi_nor_read_sr(nor, &sr_cr[0]); @@ -2256,7 +2256,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor) * When the configuration register Quad Enable bit is one, only the * Write Status (01h) command with two data bytes may be used. */ - if (sr_cr[1] & CR_QUAD_EN_SPAN) { + if (sr_cr[1] & SR2_QUAD_EN_BIT1) { ret = spi_nor_read_sr(nor, &sr_cr[0]); if (ret) return ret; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d6ec55cc6d97..f626e0e52909 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -144,10 +144,8 @@ #define FSR_P_ERR BIT(4) /* Program operation status */ #define FSR_PT_ERR BIT(1) /* Protection error bit */ -/* Configuration Register bits. */ -#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ - /* Status Register 2 bits. */ +#define SR2_QUAD_EN_BIT1 BIT(1) #define SR2_QUAD_EN_BIT7 BIT(7) /* Supported SPI protocols */ -- 2.9.5 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/