Re: [PATCH v4 2/3] spi-nor: s25fl512s supports region locking

[<Tudor.Ambarus@xxxxxxxxxxxxx>]

Hi, Geert,

On 05/08/2019 04:11 PM, Geert Uytterhoeven wrote:
> External E-Mail
> 
> 
> Hi Tudor,
> 
> On Wed, May 8, 2019 at 12:44 PM <Tudor.Ambarus@xxxxxxxxxxxxx> wrote:
>> Would you run this debug patch on top of mtd/next? I dumped the SR and CR before
>> and after the operations in cause.
> 
> Thanks, giving it a try...
> 
>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
>> index 73172d7f512b..20d0fdb1dc92 100644
>> --- a/drivers/mtd/spi-nor/spi-nor.c
>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> @@ -22,6 +22,8 @@
>>  #include <linux/spi/flash.h>
>>  #include <linux/mtd/spi-nor.h>
>>
>> +#define DEBUG
> 
> Should be moved to the top of the file, before dev_dbg() is defined.
> 
> Result is:
> 
> m25p80 spi0.0: bfpt.dwords[1] = ffffffff
> m25p80 spi0.0: bfpt.dwords[2] = ffffffff
> m25p80 spi0.0: bfpt.dwords[3] = ffffffff
> m25p80 spi0.0: bfpt.dwords[4] = ffffffff
> m25p80 spi0.0: bfpt.dwords[5] = ffffffff
> m25p80 spi0.0: bfpt.dwords[6] = ffffffff
> m25p80 spi0.0: bfpt.dwords[7] = ffffffff
> m25p80 spi0.0: bfpt.dwords[8] = ffffffff
> m25p80 spi0.0: bfpt.dwords[9] = ffffffff
> m25p80 spi0.0: bfpt.dwords[10] = 00000000
> m25p80 spi0.0: bfpt.dwords[11] = 00000000
> m25p80 spi0.0: bfpt.dwords[12] = 00000000
> m25p80 spi0.0: bfpt.dwords[13] = 00000000
> m25p80 spi0.0: bfpt.dwords[14] = 00000000
> m25p80 spi0.0: bfpt.dwords[15] = 00000000
> m25p80 spi0.0: bfpt.dwords[16] = 00000000
> m25p80 spi0.0: failed to parse BFPT: err = -22
> m25p80 spi0.0: spi_nor_init_params sfdp parse failed, ret =-22
> m25p80 spi0.0: SR = 00000000
> m25p80 spi0.0: CR = 00000002
> m25p80 spi0.0: Erase Error occurred
> m25p80 spi0.0: timeout while writing SR, ret = -5
> m25p80 spi0.0: SR = 000000ff
> m25p80 spi0.0: CR = 000000ff

ff can mean that the lines are "in air", maybe the flash resets when we
write_sr(nor, 0)? How about adding a delay here to let the flash reset?

SR=0 and CR=2 after reset, both write_sr(nor, 0) and quad_enable can be avoided
-> read SR, clear BP bits only if they are set to 1, read CR -> set Quad Enable
bit only when it's zero.

Cheers,
ta

> m25p80 spi0.0: SR and CR before quad_enable:
> m25p80 spi0.0: SR = 000000ff
> m25p80 spi0.0: CR = 000000ff
> m25p80 spi0.0: Erase Error occurred
> m25p80 spi0.0: timeout while writing configuration register
> m25p80 spi0.0: SR and CR after quad_enable:
> m25p80 spi0.0: SR = 000000ff
> m25p80 spi0.0: CR = 000000ff
> m25p80 spi0.0: quad mode not supported, err = -5
> m25p80: probe of spi0.0 failed with error -5
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
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