Hello Miquel Raynal <miquel.raynal@xxxxxxxxxxx> wrote on Wed, 3 Oct 2018 11:05:04 +0200: > With the current implementation, the complete() in the IRQ handler is > supposed to be called only if the register status has one or the other > RDY bit set. Other events might trigger an interrupt as well if > enabled, but should not end-up with a complete() call. > > For this purpose, the code was checking if the other bits were set, in > this case complete() was not called. This is wrong as two events might > happen in a very tight time-frame and if the NDSR status read reports > two bits set (eg. RDY(0) and RDDREQ) at the same time, complete() was > not called. > > This logic would lead to timeouts in marvell_nfc_wait_op() and has > been observed on PXA boards (NFCv1) in the Hamming write path. > > Fixes: 02f26ecf8c77 ("mtd: nand: add reworked Marvell NAND controller driver") > Cc: stable@xxxxxxxxxxxxxxx > Reported-by: Daniel Mack <daniel@xxxxxxxxxx> > Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> > Tested-by: Daniel Mack <daniel@xxxxxxxxxx> > --- > drivers/mtd/nand/raw/marvell_nand.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c > index bc2ef5209783..c7573ccdbacd 100644 > --- a/drivers/mtd/nand/raw/marvell_nand.c > +++ b/drivers/mtd/nand/raw/marvell_nand.c > @@ -686,7 +686,7 @@ static irqreturn_t marvell_nfc_isr(int irq, void *dev_id) > > marvell_nfc_disable_int(nfc, st & NDCR_ALL_INT); > > - if (!(st & (NDSR_RDDREQ | NDSR_WRDREQ | NDSR_WRCMDREQ))) > + if (st & (NDSR_RDY(0) | NDSR_RDY(1))) > complete(&nfc->complete); > > return IRQ_HANDLED; Applied to nand/next. ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/