Hi Wolfram Sang, Thanks for the feedback. > -----Original Message----- > From: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> > Sent: 28 February 2025 09:42 > Subject: Re: [PATCH v3 3/8] mmc: renesas_sdhi: Add support for RZ/G3E SoC > > On Thu, Feb 06, 2025 at 01:40:27PM +0000, Biju Das wrote: > > The SDHI/eMMC IPs in the RZ/G3E SoC are similar to those in R-Car Gen3. > > However, the RZ/G3E SD0 channel has Voltage level control and PWEN pin > > support via SD_STATUS register. > > > > internal regulator support is added to control the voltage levels of > > the SD pins via sd_iovs/sd_pwen bits in SD_STATUS register by > > populating vqmmc-regulator child node. > > > > SD1 and SD2 channels have gpio regulator support and internal > > regulator support. Selection of the regulator is based on the regulator phandle. > > Similar case for SD0 fixed voltage (eMMC) that uses fixed regulator > > and > > SD0 non-fixed voltage (SD0) that uses internal regulator. > > Okay, since I don't see a constant state of the regulator, let's just restore the original value as > you do here. I mean it works. OK. > > > + if (priv->rdev) > > + sd_ctrl_read32_rep(host, CTL_SD_STATUS, &sd_status, 1); > > What about introducing sd_ctrl_read32? Agreed, will introduce sd_ctrl_read32(). Cheers, Biju
