On 25/11/2024 03:20, Yuanjie Yang wrote:
> On Fri, Nov 22, 2024 at 01:35:28PM +0100, Krzysztof Kozlowski wrote:
>> On 22/11/2024 09:40, Yuanjie Yang wrote:
>>> On Fri, Nov 22, 2024 at 08:04:31AM +0100, Krzysztof Kozlowski wrote:
>>>> On 22/11/2024 07:51, Yuanjie Yang wrote:
>>>>> Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
>>>>>
>>>>> Signed-off-by: Yuanjie Yang <quic_yuanjiey@xxxxxxxxxxx>
>>>>> ---
>>>>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++
>>>>> 1 file changed, 198 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>>> index 590beb37f441..37c6ab217c96 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>>> @@ -399,6 +399,65 @@ qfprom: efuse@780000 {
>>>>> #size-cells = <1>;
>>>>> };
>>>>>
>>>>> + sdhc_1: mmc@7c4000 {
>>>>> + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
>>>>> + reg = <0x0 0x007c4000 0x0 0x1000>,
>>>>> + <0x0 0x007c5000 0x0 0x1000>;
>>>>> + reg-names = "hc",
>>>>> + "cqhci";
>>>>> +
>>>>> + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
>>>>> + interrupt-names = "hc_irq",
>>>>> + "pwr_irq";
>>>>> +
>>>>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>>>>> + <&gcc GCC_SDCC1_APPS_CLK>,
>>>>> + <&rpmhcc RPMH_CXO_CLK>,
>>>>> + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
>>>>> + clock-names = "iface",
>>>>> + "core",
>>>>> + "xo",
>>>>> + "ice";
>>>>> +
>>>>> + resets = <&gcc GCC_SDCC1_BCR>;
>>>>> +
>>>>> + power-domains = <&rpmhpd RPMHPD_CX>;
>>>>> + operating-points-v2 = <&sdhc1_opp_table>;
>>>>> + iommus = <&apps_smmu 0x02c0 0x0>;
>>>>> + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
>>>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>>>>> + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
>>>>> + interconnect-names = "sdhc-ddr",
>>>>> + "cpu-sdhc";
>>>>> +
>>>>> + bus-width = <8>;
>>>>> + qcom,dll-config = <0x000f642c>;
>>>>> + qcom,ddr-config = <0x80040868>;
>>>>> + supports-cqe;
>>>>> + dma-coherent;
>>>>> + mmc-ddr-1_8v;
>>>>> + mmc-hs200-1_8v;
>>>>> + mmc-hs400-1_8v;
>>>>> + mmc-hs400-enhanced-strobe;
>>>>
>>>> These are properties of memory, not SoC. If the node is disabled, means
>>>> memory is not attached to the SoC, right?
>>>>
>>>>> + status = "disabled";
>>> Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc,
>>> they are memory configurations that need to be written to the ioaddr.
>>> And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config,
>>> they indicate the bus speed at which the host contoller can operate.
>>> If the node is disabled, which means Soc don't support these properties.
>> No, that is not the meaning of node is disabled. When node is disabled,
>> it means board does not have attached memory.
>>
>> Move the memory related properties to the board.
>
> Thanks, Ok I understand, I will move the memory related
> properties(qcom,dll-config and qcom,ddr-config) to the
> board dts in next version.
What? Why are you talking about these properties? My comment was not
under these!
Best regards,
Krzysztof
