On 10/11/2023 09:11, Sai Krishna Potthuri wrote: > From: Swati Agarwal <swati.agarwal@xxxxxxx> > Please use subject prefixes matching the subsystem. You can get them for example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory your patch is touching. It's: dt-bindings > Add gate property in example node for Xilinx platforms which will be used > to ungate the DLL clock. DLL clock is required for higher frequencies like > 50MHz, 100MHz and 200MHz. > DLL clock is automatically selected by the SD controller when the SD > output clock frequency is more than 25 MHz. > > Signed-off-by: Swati Agarwal <swati.agarwal@xxxxxxx> > Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@xxxxxxx> > Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@xxxxxxx> > --- > Note: This patch only updates the example nodes with the gate property for > Xilinx platforms. > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
