在 2023/11/3 19:15, Ulf Hansson 写道:
+ Anand On Tue, 10 Oct 2023 at 18:44, Ziyang Huang <hzyitc@xxxxxxxxxxx> wrote:Commit 4bc31edebde5 ("mmc: core: Set HS clock speed before sending HS CMD13") set HS clock (52MHz) before switching to HS mode. For this freq, FCLK_DIV5 will be selected and div value is 10 (reg value is 9). Then we set rx_clk_phase to 11 or 15 which is out of range and make hardware frozen. After we send command request, no irq will be interrupted and the mmc driver will keep to wait for request finished, even durning rebooting. So let's set it to Phase 90 which should work in most cases. Then let meson_mx_sdhc_execute_tuning() to find the accurate value for data transfer. If this doesn't work, maybe need to define a factor in dts. Fixes: e4bf1b0970ef ("mmc: host: meson-mx-sdhc: new driver for the Amlogic Meson SDHC host") Signed-off-by: Ziyang Huang <hzyitc@xxxxxxxxxxx>Let's give this a try! Although, rather than queuing it as a fix for v6.7, I am picking it for v6.8 and adding a stable tag, this should allow it to become a bit more tested first. Kind regards Uffe
Yes, I think any fixes better than now since it's broken and can't work.
