在 2023/10/29 21:08, Anand Moon 写道:
Hi Ziyang, On Tue, 10 Oct 2023 at 22:15, Ziyang Huang <hzyitc@xxxxxxxxxxx> wrote:Commit 4bc31edebde5 ("mmc: core: Set HS clock speed before sending HS CMD13") set HS clock (52MHz) before switching to HS mode. For this freq, FCLK_DIV5 will be selected and div value is 10 (reg value is 9). Then we set rx_clk_phase to 11 or 15 which is out of range and make hardware frozen. After we send command request, no irq will be interrupted and the mmc driver will keep to wait for request finished, even durning rebooting. So let's set it to Phase 90 which should work in most cases. Then let meson_mx_sdhc_execute_tuning() to find the accurate value for data transfer. If this doesn't work, maybe need to define a factor in dts. Fixes: e4bf1b0970ef ("mmc: host: meson-mx-sdhc: new driver for the Amlogic Meson SDHC host") Signed-off-by: Ziyang Huang <hzyitc@xxxxxxxxxxx> --- Changes since v1: Use Phase 90 instand of value 1I have tested this patch on my Odroid C1+ board. Please add my Tested-by: Anand Moon <linux.amoon@xxxxxxxxx> [alarm@alarm ~]$ sudo cat /sys/kernel/debug/mmc1/ios clock: 100000000 Hz actual clock: 94444445 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 9 (mmc HS200) signal voltage: 1 (1.80 V) driver type: 0 (driver type B) [alarm@alarm ~]$ sync && dd if=/dev/zero of=~/testfile bs=100M count=1 oflag=dsync && sync 1+0 records in 1+0 records out 104857600 bytes (105 MB, 100 MiB) copied, 5.70235 s, 18.4 MB/s [alarm@alarm ~]$ sync && dd if=~/testfile of=/dev/null bs=100M count=1 iflag=dsync && sync 1+0 records in 1+0 records out 104857600 bytes (105 MB, 100 MiB) copied, 0.20267 s, 517 MB/s Thanks -Anand
Oh, thank you.
