Re: [PATCH V1 1/1] mmc:sdhci-pci-o2micro: Fix SDR50 mode timing issue

[Ulf Hansson <ulf.hansson@xxxxxxxxxx>]

+ Adrian (corrected the email)

On Thu, 23 Feb 2023 at 13:05, <fredaibayhubtech@xxxxxxx> wrote:
>
> From: Fred <fred.ai@xxxxxxxxxxxxxx>
>
> Change SDR50 mode clock source from DLL output clock to PLL open clock
> 1.HS200 and SDR104 mode select DLL output clock
> 2.SDR50 mode select PLL open clock
>
> Signed-off-by: Fred <fred.ai@xxxxxxxxxxxxxx>

Looks like you posted this to an incorrect email to Adrian, perhaps
re-post to include him.

Kind regards
Uffe

> ---
> Change in V1
> SDR50 mode select PLL open clock as its clock source.
> ---
>  drivers/mmc/host/sdhci-pci-o2micro.c | 30 +++++++++++++++-------------
>  1 file changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index 98cadff47b2b..620f52ad9667 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -339,22 +339,24 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
>         reg_val &= ~SDHCI_CLOCK_CARD_EN;
>         sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
>
> -       /* UnLock WP */
> -       pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> -       scratch_8 &= 0x7f;
> -       pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> -
> -       /* Set pcr 0x354[16] to choose dll clock, and set the default phase */
> -       pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
> -       reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
> -       reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
> -       pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
> +       if ((host->timing == MMC_TIMING_MMC_HS200) ||
> +               (host->timing == MMC_TIMING_UHS_SDR104)) {
> +               /* UnLock WP */
> +               pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> +               scratch_8 &= 0x7f;
> +               pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
>
> -       /* Lock WP */
> -       pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> -       scratch_8 |= 0x80;
> -       pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> +               /* Set pcr 0x354[16] to choose dll clock, and set the default phase */
> +               pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
> +               reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
> +               reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
> +               pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
>
> +               /* Lock WP */
> +               pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> +               scratch_8 |= 0x80;
> +               pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> +       }
>         /* Start clk */
>         reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
>         reg_val |= SDHCI_CLOCK_CARD_EN;
> --
> 2.37.2
>