On 19/01/2023 9:58 UTC, Andy Shevchenko wrote:
>On Thu, Jan 19, 2023 at 5:52 AM Brad Larson <blarson@xxxxxxx> wrote:
>>
>> The AMD Pensando Elba SoC includes a DW apb_ssi v4 controller
>> with device specific chip-select control. The Elba SoC
>> provides four chip-selects where the native DW IP supports
>> two chip-selects. The Elba DW_SPI instance has two native
>> CS signals that are always overridden.
>
...
>
>> +struct dw_spi_elba {
>> + struct regmap *syscon;
>> +};
>
>Why can't struct regmap be used directly?
Yes it can, all that is needed is regmap. See result below.
...
>
>> +static void dw_spi_elba_override_cs(struct dw_spi_elba *dwselba, int cs, int enable)
>> +{
>> + regmap_update_bits(dwselba->syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs),
>> + ELBA_SPICS_SET(cs, enable));
>
>> +
>
>Redundant blank line.
Removed
...
>
>> + dev_err(&pdev->dev, "failed to find %s\n", syscon_name);
>> + return -ENODEV;
>
>return dev_err_probe();
Changed in both places.
...
>
>> + dev_err(&pdev->dev, "syscon regmap lookup failed\n");
>> + return PTR_ERR(regmap);
>
>Ditto.
Smaller diff with the above change and looks like this:
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -53,6 +53,20 @@ struct dw_spi_mscc {
void __iomem *spi_mst; /* Not sparx5 */
};
+/*
+ * Elba SoC does not use ssi, pin override is used for cs 0,1 and
+ * gpios for cs 2,3 as defined in the device tree.
+ *
+ * cs: | 1 0
+ * bit: |---3-------2-------1-------0
+ * | cs1 cs1_ovr cs0 cs0_ovr
+ */
+#define ELBA_SPICS_REG 0x2468
+#define ELBA_SPICS_OFFSET(cs) ((cs) << 1)
+#define ELBA_SPICS_MASK(cs) (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs))
+#define ELBA_SPICS_SET(cs, val) \
+ ((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs))
+
/*
* The Designware SPI controller (referred to as master in the documentation)
* automatically deasserts chip select when the tx fifo is empty. The chip
@@ -237,6 +251,56 @@ static int dw_spi_canaan_k210_init(struct platform_device *pdev,
return 0;
}
+static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int enable)
+{
+ regmap_update_bits(syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs),
+ ELBA_SPICS_SET(cs, enable));
+}
+
+static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
+{
+ struct dw_spi *dws = spi_master_get_devdata(spi->master);
+ struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
+ struct regmap *syscon = dwsmmio->priv;
+ u8 cs;
+
+ cs = spi->chip_select;
+ if (cs < 2)
+ dw_spi_elba_override_cs(syscon, spi->chip_select, enable);
+
+ /*
+ * The DW SPI controller needs a native CS bit selected to start
+ * the serial engine.
+ */
+ spi->chip_select = 0;
+ dw_spi_set_cs(spi, enable);
+ spi->chip_select = cs;
+}
+
+static int dw_spi_elba_init(struct platform_device *pdev,
+ struct dw_spi_mmio *dwsmmio)
+{
+ const char *syscon_name = "amd,pensando-elba-syscon";
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *node;
+ struct regmap *syscon;
+
+ node = of_parse_phandle(np, syscon_name, 0);
+ if (!node)
+ return dev_err_probe(&pdev->dev, -ENODEV, "failed to find %s\n",
+ syscon_name);
+
+ syscon = syscon_node_to_regmap(node);
+ if (IS_ERR(syscon))
+ return dev_err_probe(&pdev->dev, PTR_ERR(syscon),
+ "syscon regmap lookup failed\n");
+
+ dwsmmio->priv = syscon;
+ dwsmmio->dws.set_cs = dw_spi_elba_set_cs;
+
+ return 0;
+}
+
static int dw_spi_mmio_probe(struct platform_device *pdev)
{
int (*init_func)(struct platform_device *pdev,
@@ -352,6 +416,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
{ .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},
{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
+ { .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init},
{ /* end of table */}
};
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
Regards,
Brad
