On 10/26/22 15:50, Rob Herring wrote:
On Wed, Oct 26, 2022 at 09:16:26AM -0500, Dinh Nguyen wrote:
Document the optional "altr,sysmgr-syscon" binding that is used to
access the System Manager register that controls the SDMMC clock
phase.
Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
---
v6: make "altr,sysmgr-syscon" optional
v5: document reg shift
v4: add else statement
v3: document that the "altr,sysmgr-syscon" binding is only applicable to
"altr,socfpga-dw-mshc"
v2: document "altr,sysmgr-syscon" in the MMC section
---
.../bindings/mmc/synopsys-dw-mshc.yaml | 23 ++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
index ae6d6fca79e2..0e2024eb9018 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
@@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys Designware Mobile Storage Host Controller Binding
-allOf:
- - $ref: "synopsys-dw-mshc-common.yaml#"
-
maintainers:
- Ulf Hansson <ulf.hansson@xxxxxxxxxx>
@@ -38,6 +35,26 @@ properties:
- const: biu
- const: ciu
+allOf:
+ - $ref: synopsys-dw-mshc-common.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: altr,socfpga-dw-mshc
+ then:
+ properties:
+ altr,sysmgr-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - description: phandle to the sysmgr node
+ - description: register offset that controls the SDMMC clock phase
+ - description: register shift for the smplsel(drive in) setting
This goes in the top-level. Use if/then schema to add constraints, not
define properties.
+ else:
Then you'll need to negate the if: if: { not: { properties: ... }}
Thanks Rob, is this what you mean?
altr,sysmgr-syscon:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to the sysmgr node
- description: register offset that controls the SDMMC clock
phase
- description: register shift for the smplsel(drive in) setting
description:
Contains the phandle to System Manager block that contains
the SDMMC clock-phase control register. The first value is the
pointer
to the sysmgr, the 2nd value is the register offset for the SDMMC
clock phase register, and the 3rd value is the bit shift for the
smplsel(drive in) setting.
allOf:
- $ref: "synopsys-dw-mshc-common.yaml#"
- if:
properties:
compatible:
contains:
const: altr,socfpga-dw-mshc
then:
not: <----- add the 'not' here?
required:
- altr,sysmgr-syscon
else:
properties:
altr,sysmgr-syscon: false
