Hi, On 22.10.2021 12:53, Christian Hewitt wrote: >> On 22 Oct 2021, at 12:21 pm, Jaehoon Chung <jh80.chung@xxxxxxxxxxx> wrote: >> >> Even though there are candiates value if can't find best value, it's >> returned -EIO. It's not proper behavior. >> If there is not best value, use a first candiate value to work eMMC. >> >> Signed-off-by: Jaehoon Chung <jh80.chung@xxxxxxxxxxx> >> Tested-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx> > Tested-by: Christian Hewitt <christianshewitt@xxxxxxxxx> > > v2 patch working fine with the module that triggered the original report: > > [ 2.902144] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63) > [ 2.912118] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63) > [ 3.142474] mmc_host mmc0: Bus speed (slot 0) = 200000000Hz (slot req 200000000Hz, actual 200000000HZ div = 0) > [ 3.239339] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 52000000Hz, actual 50000000HZ div = 0) > [ 3.241388] mmc_host mmc0: Bus speed (slot 0) = 266666666Hz (slot req 200000000Hz, actual 133333333HZ div = 1) I wonder why 266666666Hz bus speed is selected instead of the 400000000Hz one. Did you remove the workaround patch which changed the divider value from your kernel tree? I didn't analyze the code, so maybe this change is intentional result of this patch? On my XU4 I get 400000000Hz bus clock for the eMMC dw-mmc controller. > [ 3.243310] mmc0: new HS400 MMC card at address 0001 > [ 3.259191] mmcblk0: mmc0:0001 8GME4R 7.28 GiB > [ 3.302621] mmcblk0: p1 p2 > [ 3.311541] mmcblk0boot0: mmc0:0001 8GME4R 4.00 MiB > [ 3.327737] mmcblk0boot1: mmc0:0001 8GME4R 4.00 MiB > [ 3.340919] mmcblk0rpmb: mmc0:0001 8GME4R 512 KiB, chardev (246:0) Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland
