On 31 October 2018 at 23:59, Niklas Söderlund <niklas.soderlund@xxxxxxxxxxxx> wrote: > From: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx> > > The driver sets an incorrect clock and depends on the clock driver > knowledge of this incorrect setting to still set a 200Mhz SDn clock. > Instead of spreading the workaround between the two drivers the clock > driver should be made aware of the ES versions where the special clock > handling is needed no need to keep this workaround in the SDHI driver. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx> Applied for next, thanks! Kind regards Uffe > --- > drivers/mmc/host/renesas_sdhi_core.c | 9 --------- > 1 file changed, 9 deletions(-) > > diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c > index d3ac43c3d0b655dc..78bd117bbe65de46 100644 > --- a/drivers/mmc/host/renesas_sdhi_core.c > +++ b/drivers/mmc/host/renesas_sdhi_core.c > @@ -163,15 +163,6 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, > if (new_clock == 0) > goto out; > > - /* > - * Both HS400 and HS200/SD104 set 200MHz, but some devices need to > - * set 400MHz to distinguish the CPG settings in HS400. > - */ > - if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && > - host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 && > - new_clock == 200000000) > - new_clock = 400000000; > - > clock = renesas_sdhi_clk_update(host, new_clock) / 512; > > for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) > -- > 2.19.1 >
