On Fri, Nov 02, 2018 at 01:42:47PM +0100, Niklas Söderlund wrote:
> Hi Simon,
>
> On 2018-11-02 12:55:02 +0100, Simon Horman wrote:
> > On Wed, Oct 31, 2018 at 11:59:44PM +0100, Niklas Söderlund wrote:
> > > From: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
> > >
> > > The driver sets an incorrect clock and depends on the clock driver
> > > knowledge of this incorrect setting to still set a 200Mhz SDn clock.
> > > Instead of spreading the workaround between the two drivers the clock
> > > driver should be made aware of the ES versions where the special clock
> > > handling is needed no need to keep this workaround in the SDHI driver.
> > >
> > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
> >
> > Does this change cause a regression pending an update
> > to the clock driver?
>
> No it does not, the corresponding BSP commit to the clock driver [1] was
> never part of upstream. This change should never have been merged
> upstream as it uses the hack from the BSP clock driver. Also HS400 have
> never been enabled upstream for Gen3.
>
> 1. 11fca067bde0221d ("clk: renesas: rcar-gen3: Fix SD divider setting")
Thanks, got it.
Reviewed-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
