On Wed, May 3, 2017 at 12:05 PM, Benoît Thébaudeau <benoit@xxxxxxxxxxx> wrote: > The eSDHC can only DMA from 32-bit-aligned addresses. > > This fixes the following test cases of mmc_test: > 11: Badly aligned write > 12: Badly aligned read > 13: Badly aligned multi-block write > 14: Badly aligned multi-block read > > Signed-off-by: Benoît Thébaudeau <benoit@xxxxxxxxxxx> Is this the right description? I thought that SDHCI_QUIRK_32BIT_DMA_ADDR was for devices that cannot address high memory above 0xffffffff, rather than requiring a specific alignment. If this is indeed an address range problem rather than an alignment problem, are you sure it is the SD controller that is wrong here, rather than having a 64-bit DMA capable SDHCI connected to a 32-bit parent bus? In the latter case, the dma-ranges property in the parent bus should limit the addressing, not the device. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html